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PIC18C252 Datasheet(PDF) 7 Page - Microchip Technology |
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PIC18C252 Datasheet(HTML) 7 Page - Microchip Technology |
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7 / 296 page  © 7/99 Microchip Technology Inc. Preliminary DS39026B-page 7 PIC18CXX2 FIGURE 1-2: PIC18C4X2 BLOCK DIAGRAM Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Instruction Decode & Control OSC1/CLKI OSC2/CLKO MCLR VDD, VSS PORTA PORTB PORTC RA4/T0CKI RA5/AN4/SS/LVDIN RB0/INT0 RB7:RB4 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Brown-out Reset Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit. 2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent. Addressable CCP1 Master Timer0 Timer1 Timer2 Serial Port RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0 Parallel Slave Port Timing Generation 4X PLL A/D Converter RB1/INT1 Data Latch Data RAM (up to 4K address reach) Address Latch Address<12> 12 (2) Bank0, F BSR FSR0 FSR1 FSR2 4 12 4 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODL PRODH 8 x 8 Multiply WREG 8 BIT OP 8 8 ALU<8> 8 Address Latch Program Memory (up to 2M Bytes) Data Latch 20 21 21 16 8 8 8 inc/dec logic 21 8 Data Bus<8> TABLELATCH 8 Instruction 12 3 ROMLATCH Timer3 PORTD PORTE RD7/PSP7:RD0/PSP0 RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS CCP2 RB2/INT2 RB3/CCP2(1) T1OSI T1OSO PCLATU PCU RA6 Precision Reference Voltage Synchronous USART Register 8 Table Pointer <2> inc/dec logic Decode |
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