LP3852, LP3855

www.ti.com

SNVS174I – FEBRUARY 2003 – REVISED FEBRUARY 2015

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Lead temperature (soldering, 5 sec.)

260

°C

Internally limited

Input supply voltage (survival)

–0.3

7.5

Shutdown input voltage (survival)

–0.3

7.5

V

–0.3

6

Short-circuit protected

Maximum voltage for ERROR pin

Maximum voltage for SENSE pin

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be

Implementation section.

(3)

If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.

(4)

The output PMOS structure contains a diode between the IN and OUT terminals. This diode is normally reverse biased. This diode will

get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can

typically withstand 200 mA of DC current and 1 A of peak current.

8.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

2.5

7

V

Shutdown input voltage

−0.3

7

Maximum operating current (DC)

1.5

A

Junction temperature

−40

125

°C

(1)

8.4 Thermal Information

LP3852/LP3855

NDC

KTT

NDH

UNIT

5 PINS

5 PINS

5 PINS

Junction-to-ambient thermal resistance, High-K

65.2

40.3

32

Junction-to-case (top) thermal resistance

47.2

43.4

43.8

Junction-to-board thermal resistance

9.9

23.1

18.6

°C/W

Junction-to-top characterization parameter

3.4

11.5

8.8

Junction-to-board characterization parameter

9.7

22

18

Junction-to-case (bottom) thermal resistance

N/A

1

1.2

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Copyright © 2003–2015, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Links: LP3852 LP3855