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TC520A Datasheet(PDF) 5 Page - Microchip Technology |
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TC520A Datasheet(HTML) 5 Page - Microchip Technology |
5 / 16 page © 2002 Microchip Technology Inc. DS21431B-page 5 TC520A 12 14 LOAD Input, active low; level and edge triggered. The LOAD VALUE is clocked into the 8-bit shift register on board the TC520A while LOAD is held low. The LOAD VALUE is then transferred into the TC520A internal timebase counter (and becomes effective) when LOAD is returned high. If so desired, LOAD can be momentarily pulsed low, eliminating the needtoclock aLOAD VALUE into DIN. In this case, the current state of DIN is clocked into the TC520A timebase counter selecting either a count of 65536 (DIN = High), or count of 32768, (DIN =Low). 13 15 DV Output, active low. DV is brought low any time the TC520A is in the AZ phase of con- version. This occurs when, either the TC520A initiates a normal AZ phase by setting A, B, equal to 01, or when CE is pulled high, which overrides the normal A, B sequencing andforcesanAZ state. DV is returned high when the TC520A exits AZ. 14 16 CE Input, active low, level triggered. Conversion will be continuously performed as long as CE remains low. Pulling CE high causes the conversion process to be halted and forces the TC520A into the AZ mode for as long as CE remains high. CE should be taken high whenever it is necessary to momentarily suspend conversion (for example: to change the address lines of an input multiplexer). CE should be pulled high only when the TC520A enters an AZ phase (i.e. when DV is low). This is necessary to avoid excessively long integrator discharge times, which could result in erroneous conver- sion. This pin should be grounded if unused. It should be left floating if a 0.01 µF RESET capacitor is connected to it (see Section 4.0, Typical Applications). TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number 14-Pin PDIP Pin Number 16-Pin SOIC Symbol Description |
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