W958D6DB

256Mb Async./Burst/Sync./A/D MUX

Publication Release Date : June 27 ,2013

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Revision : A01-003

TABLE OF CONTENTS

1. GENERAL DESCRIPTION .......................................................................................................... 1

2. FEATURES.................................................................................................................................. 1

3. ORDERING INFORMATION ....................................................................................................... 2

4. PIN CONFIGURATION................................................................................................................ 5

4.1 Ball Assignment .................................................................................................................................. 5

5. PIN DESCRIPTION ..................................................................................................................... 6

5.1 Signal Description............................................................................................................................... 6

6. BLOCK DIAGRAM ...................................................................................................................... 7

7. INSTRUCTION SET .................................................................................................................... 8

7.1 Bus Operation..................................................................................................................................... 8

8. FUNCTIONAL DESCRIPTION .................................................................................................... 9

8.1 Power Up Initialization ........................................................................................................................ 9

8.1.1 Power-Up Initialization Timing ................................................................................................................... 9

8.2 Bus Operating Modes ......................................................................................................................... 9

8.2.1 Asynchronous Modes ................................................................................................................................ 9

8.2.1.1 READ Operation (ADV# LOW)....................................................................................................................... 10

8.2.1.2 WRITE Operation (ADV# LOW) ..................................................................................................................... 10

8.2.2 Burst Mode Operation.............................................................................................................................. 11

8.2.2.1 Burst Mode READ (4-word burst)................................................................................................................... 11

8.2.2.2 Burst Mode WRITE (4-word burst) ................................................................................................................. 12

8.2.2.3 Refresh Collision During Variable-Latency READ Operation ......................................................................... 13

8.2.3 Mixed-Mode Operation ............................................................................................................................ 14

8.2.4 WAIT Operation ....................................................................................................................................... 14

8.2.4.1 Wired-OR WAIT Configuration ....................................................................................................................... 14

8.2.5 LB#/ UB# Operation................................................................................................................................. 15

8.3 Low Power Operation ....................................................................................................................... 15

8.3.1 Standby Mode Operation......................................................................................................................... 15

8.3.2 Temperature Compensated Refresh ....................................................................................................... 15

8.3.3 Partial-Array Refresh ............................................................................................................................... 15

8.3.4 Deep Power-Down Operation.................................................................................................................. 15

8.4 Registers........................................................................................................................................... 16

8.4.1 Access Using CRE .................................................................................................................................. 16

8.4.1.1 Configuration Register WRITE Asynchronous Mode Followed by READ Operation ...................................... 17

8.4.1.2 Configuration Register WRITE Synchronous Mode Followed by READ Operation........................................ 18

8.4.1.3 Register READ Asynchronous Mode Followed by READ ARRAY Operation ................................................. 19

8.4.1.4 Register READ Synchronous Mode Followed by READ ARRAY Operation................................................... 20

8.4.2 Software Access ...................................................................................................................................... 21

8.4.2.1 Load Configuration Register........................................................................................................................... 21

8.4.2.2 Read Configuration Register .......................................................................................................................... 22

8.4.3 Bus Configuration Register...................................................................................................................... 22

8.4.3.1 Bus Configuration Register Definition............................................................................................................. 23

8.4.3.2 Burst Length (BCR[2:0]) Default = Continuous Burst ..................................................................................... 24

8.4.3.3 Burst Wrap (BCR[3]) Default = No Wrap ........................................................................................................ 24

8.4.3.4 Sequence and Burst Length........................................................................................................................... 25

8.4.3.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength........................................................... 26

8.4.3.6 Table of Drive Strength ................................................................................................................................... 26

8.4.3.7 WAIT Configuration. (BCR[8]) ........................................................................................................................ 26

8.4.3.8 WAIT Polarity (BCR[10])................................................................................................................................. 26

8.4.3.9 WAIT Configuration During Burst Operation................................................................................................... 27

8.4.3.10 Latency Counter (BCR[13:11]) Default = Three Clock Latency .................................................................... 27

8.4.3.11 Initial Access Latency (BRC[14]) Default = Variable ..................................................................................... 27

8.4.3.12 Allowed Latency Counter Settings in Variable Latency Mode....................................................................... 27

8.4.3.13 Latency Counter (Variable Initial Latency, No Refresh Collision).................................................................. 28

8.4.3.14 Allowed Latency Counter Settings in Fixed Latency Mode........................................................................... 28

8.4.3.15 Latency Counter (Fixed Latency) ................................................................................................................. 29