5087 series

SEIKO NPC CORPORATION - 2

PAD LAYOUT

(Unit:

m)

Chip size: 1.20mm×1.10mm

Chip thickness: 180

m , 300m

PAD size: 80

m×80m(PAD No.2, 3, 4, 5, 7, 9 pins)

80

m×150m(PAD No.6, 8 pins)

110

m×80m(PAD No.10, 11 pins)

80

m×134m(PAD No.1 pin)

Chip base: GND potential

1

23

4

5

6

7

8

9

10

11

VCC1

XIN XOUT GND1

GND2

OE

VCC2

OUTN

OUT

(0,0)

(-600,-550)

(600,550)

X

Y

VCC1

VCC2

PIN DESCRIPTION and PAD COORDINATES

PAD coordinate [

m]

No.

Name

i/o

*1

Function

X

Y

1

-

-395

-424

2

-

(+) supply pin （for oscillation circuit）

-290

-440

3

XIN

i

Oscillator input pin

-72

-440

4

XOUT

o

Oscillator output pin

107

-440

5

-

(-) ground pin （for oscillation circuit）

290

-440

6

-

(-) ground pin （for all circuits excluding oscillation circuit）

395

-440

7

OE

i

Output enable pin. Outputs are high impedance when LOW

(oscillator stopped). Power-saving pull-up resistor built-in.

377

440

8

-

190

440

9

-

(+) supply pin （for all circuits excluding oscillation circuit）

85

440

10

OUTN

o

LVDS complementary output pin. Disable: High impedance

-114

440

11

OUT

o

LVDS output pin. Disable: High impedance

-380

440

*1. i: input, o: output

*2. Connect both of pins by wire-bonding for good characteristics.

*3. GND1 and GND2 pins should be connected by wire-bonding since they are disconnected.