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TPS7A1601DRBT Datasheet(PDF) 6 Page - Texas Instruments |
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TPS7A1601DRBT Datasheet(HTML) 6 Page - Texas Instruments |
6 / 32 page TPS7A16 SBVS171F – DECEMBER 2011 – REVISED OCTOBER 2015 www.ti.com 6.4 Thermal Information TPS7A1601 THERMAL METRIC(1) DGN (HVSSOP) DRB (VSON) UNIT 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 66.2 44.5 °C/W RθJC(top) Junction-to-case(top) thermal resistance 45.9 49.5 °C/W RθJB Junction-to-board thermal resistance 34.6 11.3 °C/W ψJT Junction-to-top characterization parameter 1.9 0.7 °C/W ψJB Junction-to-board characterization parameter 34.3 11.2 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance 14.9 4.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range 3 60 V VREF Internal reference TJ = 25°C, VFB = VREF, VIN = 3 V, IOUT = 10 μA 1.169 1.193 1.217 V VUVLO Undervoltage lockout threshold 2.7 V Output voltage range VIN ≥ VOUT(NOM) + 0.5 V VREF 18.5 V Nominal accuracy TJ = 25°C, VIN = 3 V, IOUT = 10 μA –2% 2% VOUT VOUT VOUT(NOM) + 0.5 V ≤ VIN ≤ 60 V (1) Overall accuracy –2% 2% VOUT 10 µA ≤ IOUT ≤ 100 mA ΔVO(ΔVI) Line regulation 3 V ≤ VIN ≤ 60 V ±1% VOUT ΔVO(ΔIO) Load regulation 10 µA ≤ IOUT ≤ 100 mA ±1% VOUT VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 20 mA 60 mV VDO Dropout voltage VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 100 mA 265 500 mV ILIM Current limit VOUT = 90% VOUT(NOM), VIN = 3 V 101 225 400 mA 3 V ≤ VIN ≤ 60 V, IOUT = 10 µA 5 15 μA IGND Ground current IOUT = 100 mA 5 μA ISHDN Shutdown supply current VEN = 0.4 V 0.59 5 μA I FB Feedback current(2) –0.1 –0.01 0.1 µA IEN Enable current 3 V ≤ VIN ≤ 12 V, VIN = VEN –1 –0.01 1 μA VEN_HI Enable high-level voltage 1.2 V VEN_LO Enable low- level voltage 0.3 V OUT pin floating, VFB increasing, VIN ≥ VIN_MIN 85% 95% VOUT VIT PG trip threshold OUT pin floating, VFB decreasing, VIN ≥ VIN_MIN 83% 93% VOUT VHYS PG trip hysteresis 2.3% 4% VOUT VPG, LO PG output low voltage OUT pin floating, VFB = 80% VREF, IPG= 1mA 0.4 V IPG, LKG PG leakage current VPG= VOUT(NOM) –1 1 μA IDELAY DELAY pin current 1 2 μA VIN = 3 V, VOUT(NOM) = VREF, COUT = 10 μF, PSRR Power-supply rejection ratio 50 dB f = 100 Hz Shutdown, temperature increasing 170 °C TSD Thermal shutdown temperature Reset, temperature decreasing 150 °C Operating junction temperature TJ –40 125 °C range (1) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT = (24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking. (2) IFB > 0 flows out of the device. 6 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TPS7A16 |
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