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FEDL9472-02 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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FEDL9472-02 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 18 page FEDL9472-02 LAPIS Semiconductor ML9472 10/18 COM_A, COM_B In the select mode, a signal in phase with the COM_OUT signal is output at “H” (VDD) and “L” (VLC2). In the non-select mode a voltage is output at “M” (VLC1). In the select mode of COM_A (non-select mode of COM_B), signals that correspond to the 1 st-to 60th-bit data of the data latch are output to the segment outputs. In the select mode of COM_B (non-select mode of COM_A), signals that correspond to the 61 st- to 120th-bit data of the data latch are output to the segment outputs. SEGn Truth Table Mode Display data in LatchA Display data in LatchB COMA COMB SEGn — “H” “H” 0 1 — “L” “L” 1 — “H” “H” 1 Static 0 — “L” “L” 0 “H” “M” 0 “L” “M” 1 “M” “H” 0 1 1 “M” “L” 1 “H” “M” 0 “L” “M” 1 “M” “H” 1 1 0 “M” “L” 0 “H” “M” 1 “L” “M” 0 “M” “H” 0 0 1 “M” “L” 1 “H” “M” 1 “L” “M” 0 “M” “H” 1 1/2 duty Dynamic 0 0 “M” “L” 0 *Note: “H” = VDD; “M” = VLC1; “L” = VLC2. |
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