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TPS717-Q1 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS717-Q1 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 34 page  IN N/C (1) EN 6 5 4 OUT GND NR/FB 1 2 3 OUT NR/FB IN GND EN 1 2 3 4 5 IN N/C (1) EN 6 5 4 OUT NR/FB GND 1 2 3 GND TPS717-Q1 SLVSBM4B – SEPTEMBER 2012 – REVISED DECEMBER 2014 www.ti.com 5 Pin Configuration and Functions DCK Package DRV Package SOT-5 2-mm × 2-mm WSON (Top View) (Top View) N/C = No connection DSE Package 1.5-mm × 1.5-mm WSON (Top View) Pin Functions PIN NO. I/O DESCRIPTION NAME DCK DRV DSE Driving the enable pin (EN) above VEN(high) turns on the regulator. EN 3 4 4 I Driving this pin below VEN(low) puts the regulator into standby mode, thereby disabling the output and reducing operating current. Adjustable voltage version only. The voltage at this pin is fed to the FB 4 2 3 I error amplifier. A resistor divider from OUT to FB sets the output voltage when in regulation. GND 2 3 2 — Ground Input to the device. A 0.1- μF to 1-μF capacitor is recommended for IN 1 6 6 I better performance. Not connected. This pin can be tied to ground to improve thermal N/C — 5 5 — dissipation. Fixed voltage versions only. An external capacitor connected to this NR 4 2 3 — pin bypasses noise generated by the internal band gap, thus lowering output noise. This pin is the regulated output voltage. A minimum capacitance of OUT 5 1 1 O 1 μF is required for stability from this pin to ground. 4 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: TPS717-Q1 |
Similar Part No. - TPS717-Q1_15 |
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Similar Description - TPS717-Q1_15 |
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