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LM53601-Q1 Datasheet(PDF) 2 Page - Texas Instruments |
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LM53601-Q1 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 4 page 6 7 8 9 5 4 3 2 1 GND 10 SW BOOT VCC FB AGND /RESET EN VIN SYNC/ MODE GND 6 7 8 9 5 4 3 2 1 GND 10 SW BOOT VCC FB BIAS /RESET EN VIN SYNC/ MODE GND LM53600-Q1, LM53601-Q1 SNAS660 – JUNE 2015 www.ti.com 4 Pin Configuration and Functions DSX Package DSX Package 10-Pin WSON 10-Pin WSON Fixed Version Top View Adjustable Version Top View Pin Functions PIN I/O(1) DESCRIPTION NAME NO. 1 SW P Regulator switch node. Connect to output inductor. High-gate driver upper supply rail. Connect a 100nF capacitor from SW pin to BOOT. An 2 BOOT I internal diode charges the capacitor while SW node is low. Internal 3V regulator output. Used as supply to internal control circuits. Connect a high 3 VCC P quality 1.0 μF capacitor from this pin to AGND for fixed versions or to GND for adjustable versions. FB (Fixed Fixed version only, this pin serves as feedback for output voltage as well as power source for I/P Versions) VCC’s regulator. Connect to output node. Bypass immediately adjacent to this pin to AGND. 4 FB (ADJ ADJ version only, this pin serves as feedback for output voltage only. Connect to output I Version) through a voltage divider which determines output voltage set point. AGND (Fixed G Fixed versions only, this ground is the ground to which input signals and FB are compared. Version) 5 BIAS (ADJ Power source for VCC’s regulator. Connect to output node. Bypass immediately adjacent to P Version) this pin. Open drain reset output. Connect to suitable voltage supply through a current limiting pull up 6 RESET O resistor. High = regulator OK, Low = regulator fault. Will go low when EN = low. See detailed description. 7 EN I Enable input to regulator. High = on, Low = off. Can be connected to Vin. Do not float. Input supply to regulator. Connect input bypass capacitors directly between this pin and 8 VIN I GND. This is a multifunction mode control input which is tolerant of voltages up to input voltage. With a valid synchronization signal at this pin, the device will switch in forced PWM mode at the external clock frequency and synchronize with it at the rising edge of the clock. See the "Electrical Characteristics table" for synchronization signal specifications. With this input tied 9 SYNC/MODE I high, the device will switch at the internal clock frequency in forced PWM mode. With this input tied low, the device will switch at the internal clock frequency in AUTO mode with diode emulation at light load. Spread spectrum is disabled if there is a valid synchronization signal. Do not float. 10 GND G Bypass to VIN immediately adjacent to this pin. (1) G = Ground, I = Input, O = Output, P = Power 2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM53600-Q1 LM53601-Q1 |
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