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IPC028N03L3 Datasheet(PDF) 2 Page - Infineon Technologies AG |
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IPC028N03L3 Datasheet(HTML) 2 Page - Infineon Technologies AG |
2 / 4 page 2 OptiMOS™3PowerMOSTransistorChip IPC028N03L3 Rev.2.5,2014-07-23 Final Data Sheet PowerMOSTransistorChip Drain Gate Source 1Description •N-channelenhancementmode •FordynamiccharacterizationrefertothedatasheetofIPD060N03LG •AQL0.65forvisualinspectionaccordingtofailurecatalogue •ElectrostaticDischargeSensitiveDeviceaccordingtoMIL-STD883C •Diebond:solderedorglued •Backsidemetallization:NiVsystem •Frontsidemetallization:AlCusystem •Passivation:nitride+imide Table1KeyPerformanceParameters Parameter Value Unit V(BR)DSS 30 V RDS(on) 6.0 1) m Ω Die size 2.26 x 1.24 mm 2 Thickness 175 µm Type/OrderingCode Package Marking RelatedLinks IPC028N03L3 Chip not defined - 2ElectricalCharacteristicsonWaferLevel atTj=25°C,unlessotherwisespecified Table2 Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Drain-source breakdown voltage V(BR)DSS 30 - - V VGS=0V,ID=1mA Gate threshold voltage VGS(th) 1 - 2.2 V VDS=VGS,ID=250µA Zero gate voltage drain current IDSS - 0.1 2 µA VGS=0V,VDS=30V Gate-source leakage current IGSS - 10 100 nA VGS=20V,VDS=0V Drain-source on- resistance RDS(on) - 0.5 2) 50 3) m Ω VGS=10V,ID=2.0A Reverse diode forward on-voltage VSD - 0.86 1.1 V VGS=0V,IF=1A 1) packaged in a PG-TO263-7 (see ref. product) 2)typicalbaredieRDS(on);VGS=10V,whenusedwith4x500µmAl-wedgedoublestitchbonding 3) limited by wafer test-equipment |
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