LMR16006Y-Q1

SNVSAC1 – JUNE 2015

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8.3 Feature Description

8.3.1 Fixed Frequency PWM Control

The LMR16006Y-Q1 implements peak current mode control. The output voltage is compared through external

resistors on the FB pin to an internal voltage reference by an error amplifier which drives the internal COMP

node. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is

compared to the high side power switch current. When the power switch current reaches the level set by the

internal COMP voltage, the power switch is turned off. The internal COMP node voltage will increase and

decrease as the output current increases and decreases. The device implements a current limit by clamping the

COMP node voltage to a maximum level.

8.3.2 Bootstrap Voltage (CB)

The LMR16006Y-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the CB

and SW pins to provide the gate drive voltage for the high side MOSFET. The CB capacitor is refreshed when

the high side MOSFET is off and the low side diode conducts. To improve drop out, the LMR16006Y-Q1 is

designed to operate at 97% duty cycle as long as the CB to SW pin voltage is greater than 3 V. When the

voltage from CB to SW drops below 3 V, the high side MOSFET is turned off using an UVLO circuit which allows

the low side diode to conduct and refresh the charge on the CB capacitor. Since the supply current sourced from

the CB capacitor is low, the high side MOSFET can remain on for more switching cycles than are required to

refresh the capacitor, thus the effective duty cycle of the switching regulator is high. Attention must be taken in

maximum duty cycle applications with light load. To ensure SW can be pulled to ground to refresh the CB

capacitor, an internal circuit will charge the CB capacitor when the load is light or the device is working in dropout

condition.

8.3.3 Output Voltage Setting

The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the

front page schematic. The feedback pin voltage 0.765 V, so the ratio of the feedback resistors sets the output

100 k

8.3.4 Enable SHDN and VIN Undervoltage Lockout

LMR16006Y-Q1 SHDN pin is a high voltage tolerant input with an internal pull up circuit. The device can be

enabled even if the SHDN pin is floating. The regulator can also be turned on using 1.23 V or higher logic

signals. If the use of a higher voltage is desired due to system or other constraints, a 100 k

Ω or larger resistor is

recommended between the applied voltage and the SHDN pin to protect the device. When SHDN is pulled down

to 0 V, the chip is turned off and enters the lowest shutdown current mode. In shutdown mode the supply current

will be decreased to approximately 1 µA. If the shutdown function is not to be used the SHDN pin may be tied to

internal UVLO circuit to shutdown the output if the input voltage falls below an internally fixed UVLO threshold

level. This ensures that the regulator is not latched into an unknown state during low input voltage conditions.

The regulator will power up when the input voltage exceeds the voltage level. If there is a requirement for a

higher UVLO voltage, the SHDN can be used to adjust the system UVLO by using external resistors.

8.3.5 Current Limit

The LMR16006Y-Q1 implements current mode control which uses the internal COMP voltage to turn off the high

side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and internal COMP voltage are

compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During

overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP node

high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch

current limit.

8

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