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TPS40303, TPS40304, TPS40305

www.ti.com

SLUS964B – NOVEMBER 2009 – REVISED MAY 2015

Feature Description (continued)

7.3.4 Oscillator and Frequency Spread Spectrum (FSS)

The oscillator frequency is internally fixed. The TPS40303 operating frequency is 300 kHz, the TPS40304

operating frequency is 600 kHz, and the TPS40305 operating frequency is 1.2 MHz.

Connecting a resistor with a value of 267 k

Ω ±10% from BP to EN/SS enables the FSS feature. When the FSS is

enabled, it spreads the internal oscillator frequency over a minimum 12% window using a 25-kHz modulation

frequency with triangular profile. By modulating the switching frequency, side-bands are created. The emission

power of the fundamental switching frequency and its harmonics is distributed into smaller pieces scattered

around many sideband frequencies. The effect significantly reduces the peak EMI noise and makes it much

easier for the resultant emission spectrum to pass EMI regulations.

7.3.5 Overcurrent Protection

Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature

coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases.

With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The

accuracy of the internal current source is ±5%. Overall offset voltage, including the offset voltage of the internal

comparator and the amplifier for scale factor of 2, is limited to ±8 mV.

Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a

prebiased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the voltage

included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.

OCP level at HDRV is fixed at 450 mV with 3000-ppm temperature coefficient to help compensate for changes in

the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current

limiting.

OCP sensing at LDRV is a true inductor valley current detection, using sample and hold. Equation 2 can be used

where

•

•

•

•

•

•

(2)

•

•

table.

•

Overcurrent is sensed across both the low-side FET and the high-side FET. If the voltage drop across either FET

exceeds the OC threshold, a count increments one count. If no OC is detected on either FET, the fault counter

decrements by one count. If three OC pulses are summed, a fault condition is declared which cycles the soft-

start function in a hiccup mode. Hiccup mode consists of four dummy soft-start timeouts followed by a real one if

overcurrent condition is encountered during normal operation, or five dummy soft-start timeouts followed by a

real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the

fault condition is removed.

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