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TPS40428 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS40428 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 92 page  TPS40428 SLUSBV0A – MAY 2014 – REVISED JULY 2014 www.ti.com Electrical Characteristics (continued) TJ = –40ºC to 125ºC, VIN = VVDD = 12 V, RRT valued to produce a switching frequency (fSW) of 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVS INTERFACE VVIO ASIC I/O voltage(10) 1.8 2.5 V VVIO = 2.5 V 1.75 High-level input voltage, AVSCLK, VIH(avs) V AVSDATA VVIO = 1.8 V 1.26 VVIO = 2.5 V 0.75 Low-level input voltage, AVSCLK, VIL(avs) V AVSDATA VVIO = 1.8 V 0.54 High-level input current, AVSCLK, IIH(avs) –50 50 µA AVSDATA(10) Low-level input current, AVSCLK, IIL(avs) –50 50 µA AVSDATA(10) fAVS AVS clock frequency range 10 30 MHz MEASUREMENT SYSTEM MVOUT(rng) VOUT measurement range 0.5 3.6 V MVOUT(acc) VOUT measurement accuracy (11) VOUT = 1 V, 0°C ≤ TJ ≤ 125°C –0.8% 0.8% MIOUT(rng) IOUT measurement range (12) 0 50 A IOUT ≥ 20 A, IOUT_CAL_GAIN = 0.503 mΩ, MIOUT(acc) IOUT measurement accuracy (11) –640 640 mA 0°C ≤ TJ ≤ 125°C, smart power mode PMBus INTERFACE(13) VIH High-level input voltage, CLK, DATA, CNTL 2.1 V VIL Low-level input voltage, CLK, DATA, CNTL 0.8 IIH High-level input current, CLK, DATA, CNTL Pin voltage = 3.3 V –10 10 µA IIL Low-level input current, CLK, DATA, CNTL Pin voltage = 0 V –10 10 VOL Low-level output voltage, DATA, SMBALRT IOUT = 4 mA 0.4 V High-level output open drain leakage IOH VOUT = VBP5 0 10 µA current, DATA, SMBALRT Low-level output open drain current, DATA, IOL 4 mA SMBALRT COUT Pin capacitance, CLK, DATA(10) 1 pF fPMB PMBus operating frequency range Slave mode 10 400 kHz Bus free time between START and tBUF 1.3 STOP(10) tHD:STA Hold time after repeated START(10) 0.6 µs tSU:STA Repeated START set-up time(10) 0.6 tSU:STO STOP setup time(10) 0.6 Receive mode 0 tHD:DAT Data hold time(10) Transmit mode 300 ns tSU:DAT Data setup time(10) 100 tTIMEOUT Error signal/detect(10) 25 35 ms tLOW:MEXT Cumulative clock low master extend time(10) 10 ms tLOW:SEXT Cumulative clock low slave extend time(10) 25 ms tLOW Clock low time(10) 1.3 µs tHIGH Clock high time(10) 0.6 µs tFALL CLK/DATA fall time(10) 300 ns tRISE CLK/DATA rise time(10) 300 tRETENTION Retention of configuration parameters(10) TJ = 25°C 100 Year Write_cycles Number of nonvolatile erase/write cycles(10) TJ = 25°C 20 K cycle (10) Specified by design. Not production tested. (11) Performance verified under application conditions. (12) The actual measurement range is limited by IOUT_CAL_GAIN command. See the IOUT_CAL_GAIN (38h) section. (13) The device supports both 100-kHz and 400-kHz bus speeds. The PMBus timing parameters in this table is for operation at 400 kHz. If the PMBus operating frequency is 100 kHz, refer to SMBus specification for timing parameters. 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: TPS40428 |
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