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TPS43350-Q1 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS43350-Q1 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 33 page  TPS43350-Q1 TPS43351-Q1 www.ti.com SLVSAR7D – JUNE 2011 – REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted) NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LPM entry threshold load current ILPM_Entry as fraction of maximum set load 1% .(3) current The exit threshold is specified to be always higher 4.10 than entry threshold LPM exit threshold load current as ILPM_Exit fraction of maximum set load (3) 10% current High-Side External NMOS Gate Drivers for Buck Controller 4.11 IGX1_peak Gate driver peak current 1.5 A 4.12 rDS(on) Source and sink driver VREG = 5.8 V, IGX1 current = 200 mA 2 Ω Low-Side NMOS Gate Drivers for Buck Controller 4.13 IGX2_peak Gate-driver peak current 1.5 A 4.14 rDS(on) Source and sink driver VREG = 5.8 V, IGX2 current = 200 mA 2 Ω Error Amplifier (OTA) for Buck Converters COMPA, COMPB = 0.8 V, 4.15 GmBUCK Transconductance 0.72 1 1.35 mS source/sink = 5 µA, test in feedback loop 4.16 IPULLUP_FBx Pullup current at FBx pins FBx = 0 V 50 100 200 nA 5.0 Digital Inputs: ENA, ENB, SYNC 5.1 VIH Higher threshold VIN = 13 V 1.7 V 5.2 VIL Lower threshold VIN = 13 V 0.7 V 5.3 RIH_SYNC Resistance VSYNC = 5 V 500 k Ω Pullup current source on ENA, 5.5 IIL_ENx VENx = 0 V 0.5 2 µA ENB 6.0 Switching Parameters – Buck DC-DC Controllers 6.1 fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz 6.2 fSW_Buck Buck switching frequency RT pin: 60-k Ω external resistor 360 400 440 kHz Buck adjustable range with 6.3 fSW_adj RT pin: external resistor 150 600 kHz external resistor 6.4 fSYNC Buck synchronization range External clock input 150 600 kHz 6.5 fSS Spread-spectrum spreading TPS43351-Q1 only 5% 7.0 Internal Gate-Driver Supply Internal regulated supply VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High 5.5 5.8 6.1 V 7.1 VREG IVREG = 0 mA to 100 mA, EXTSUP = 0 V, Load regulation 0.2% 1% SYNC = High Internal regulated supply EXTSUP = 8.5 V 7.2 7.5 7.8 V 7.2 VREG(EXTSUP) IEXTSUP = 0 mA to 125 mA, SYNC = High Load regulation 0.2% 1% EXTSUP = 8.5 V to 13 V EXTSUP switch-over voltage IVREG = 0 mA to 100 mA , 7.3 VEXTSUP_th 4.4 4.6 4.8 V threshold EXTSUP ramping positive 7.4 VEXTSUP-Hys EXTSUP switch-over hysteresis 150 250 mV 7.5 IREG-Limit Current limit on VREG EXTSUP = 0 V, normal mode as well as LPM 100 400 mA IREG_EXTSUP- Current limit on VREG when using IVREG = 0 mA to 100 mA, 7.6 125 400 mA Limit EXTSUP EXTSUP = 8.5 V, SYNC = High 8.0 Soft Start 8.1 ISSx Soft-start source current SSA and SSB = 0 V 0.75 1 1.25 µA 9.0 Oscillator (RT) 9.1 VRT Oscillator reference voltage 1.2 V 10.0 Power-Good / Delay 10.1 PGpullup Pullup for A and B to Sx2 50 k Ω 10.2 PGth1 Power-good threshold FBx falling –5% –7% –9% 10.3 PGhys Hysteresis 2% 10.4 PGdrop Voltage drop IPGA = 5 mA 450 mV 10.5 IPGA = 1 mA 100 mV 10.6 PGleak Leakage VSx2 = VPGx = 13 V 1 µA (3) The exit threshold specification is to be always higher than the entry threshold. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS43350-Q1 TPS43351-Q1 |
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