1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

AGND

VSENSE

COMP

PWRGD

BOOT

PH

PH

PH

PH

PH

RT

SYNC

SS/ENA

VBIAS

VIN

VIN

VIN

PGND

PGND

PGND

TPS54110

www.ti.com

SLVS500C

– DECEMBER 2003 – REVISED FEBRUARY 2011

PIN ASSIGNMENTS

PWP PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

NO.

AGND

1

Analog ground

—internally connected to the sensitive analog-ground circuitry. Connect to PGND and PowerPAD.

Bootstrap input. 0.022-

µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

BOOT

5

high-side FET driver.

COMP

3

Error amplifier output. Connect compensation network from COMP to VSENSE.

Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper

PGND

11

–13

areas to the input and output supply returns, and negative terminals of the input and output capacitors. Connect to

AGND and PowerPAD.

PH

6

–10

Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.

Power-good open drain output. High when VSENSE

≥ 93% Vref, otherwise PWRGD is low. Note that output is low

PWRGD

4

when SS/ENA is low or internal shutdown signal active.

RT

20

Slow-start/enable input/output. Dual-function pin that provides logic input to enable/disable device operation and

SS/ENA

18

capacitor input to externally set the start-up time.

Synchronization input. Dual-function pin that provides logic input to synchronize to an external oscillator or pin select

SYNC

19

between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be

connected to the RT pin.

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a

VBIAS

17

high quality, low ESR 0.1-

µF to 1.0-µF ceramic capacitor.

Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to

VIN

14

–16

device package with a high quality, low ESR 1-

µF to 10-µF ceramic capacitor.

VSENSE

2

Error amplifier inverting input.

© 2003–2011, Texas Instruments Incorporated

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Product Folder Link(s): TPS54110