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TPS54612 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS54612 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AGND VSENSE NC PWRGD BOOT PH PH PH PH PH PH PH PH PH RT FSEL SS/ENA VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND THERMAL PAD TPS54611, TPS54612, TPS54613 TPS54614, TPS54615, TPS54616 www.ti.com SLVS400D – AUGUST 2001 – REVISED JANUARY 2015 5 Pin Configuration and Functions TPS5461x PWP Package 28-Pin HTSSOP Top View Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. AGND 1 G Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND. BOOT 5 S Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-set FET driver. FSEL 27 I Frequency select input. Provides logic input to select between two internally set switching frequencies. NC 3 – No connection PGND 15 −19 G Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. PH 6 −14 O Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. PWRGD 4 O Powergood open-drain output. High-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active. RT 28 I Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. SS/ENA 26 I Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. VBIAS 25 S Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-µF to 1-µF ceramic capacitor. VIN 20 −24 I Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor. VSENSE 2 I Error amplifier inverting input. Connect directly to output voltage sense point. (1) I = Input, O = Output, S = Supply, G = Ground Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS54611 TPS54612 TPS54613 TPS54614 TPS54615 TPS54616 |
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