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ML2751DT Datasheet(PDF) 5 Page - Micro Linear Corporation

Part # ML2751DT
Description  Power Amplifier and LNA
Download  10 Pages
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Manufacturer  MICRO-LINEAR [Micro Linear Corporation]
Direct Link  http://www.microlinear.com
Logo MICRO-LINEAR - Micro Linear Corporation

ML2751DT Datasheet(HTML) 5 Page - Micro Linear Corporation

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ML2751
5
January, 2000
PRELIMINARY
PRELIMINARY DATASHEET
PIN DESCRIPTIONS (continued)
Pin #
Signal Name
I/O
Description
PIN Diode Driver Section
12
PIN
O (analog)
This output is a low impedance voltage source that switches between
VCC and GND to drive an external PIN diode switch. This totem pole
output is tri-stated when FEEN = 0. When active it pulls either to VCC
(if PAON = 1) or to GND (if PAON = 0), and has a nominal output
impedance of 50
W when sourcing and 120W when sinking
13
PINB
O (analog)
This output is a low impedance voltage source that switches between
VCC and GND to drive an external PIN diode switch. This totem pole
output is tri-stated when FEEN = 0. When active it pulls either to VCC
(if PAON = 0) or to GND (if PAON = 1) , and has a nominal output
impedance of 50
W when sourcing and 120W when sinking. PINB is the
complement of PIN, providing a bipolar drive for PIN diodes from a
single power rail
Control and Interface
1
PAON
I (CMOS)
Power Amplifier on pin. The PA is active when PAON = 1, and the LNA
is active when PAON = 0. Rising and falling edges of this signal
initiate a controlled ramp of the PA bias circuits to eliminate AM
generated sidebands on the transmitter output. The PIN diode drivers
are synchronized with PAON (see Figure 3). When the ML2751 is in
standby mode this pin has no effect
2
FEEN
I (CMOS)
Front-end enable. FEEN is the master power down pin. When FEEN = 0
the ML2751 is in standby mode. When FEEN = 1 either the PA or the
LNA is enabled (determined by the state of PAON). See Figure 3
Power & Ground
15
VCC
Power
Positive power supply for the LNA, the first stages of the PA, the PIN
diode drivers, and the control logic. Care should be exercised in PCB
layout to minimize the trace length, and the inductance and resistance
both in the connection to the capacitor and from the capacitor to
ground
4
GND
Ground
6
GND
Ground
7
GND
Ground
8
GND
Ground
14
GND
Ground
16
GND
Ground
17
GND
Ground
19
GND
Ground
20
GND
Ground


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