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ML4428CP Datasheet(PDF) 11 Page - Micro Linear Corporation |
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ML4428CP Datasheet(HTML) 11 Page - Micro Linear Corporation |
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11 / 16 page  11 ML4428 START-UP SEQUENCING When the motor is initially at rest, it is generating no back-EMF. Because a back-EMF signal is required for closed loop commutation, the motor must be started by other means until a velocity sufficient to generate some back-EMF is attained. Start For RCVCO voltages of less than 0.6V the ML4428 will send 6 sample pulses to the motor to determine the rotor position and drive the proper windings to produce desired rotation. This will result in motor acceleration until the RCVCO pin achieves 0.6V and closed loop operation begins. This technique results in zero reverse rotation and minimizes start-up time. The sample time pulses are set by CSNS and the initial sample interval is set by RINIT. This sense technique is not effective for air core motors, since a minimum of 30% inductance difference must occur when the motor moves. Direction The direction of motor rotation is controlled by the commutation states as given in Table 1. The state sequence is controlled by the F/R. Run When the RCVCO pin exceeds 0.6V the device will enter run mode. At this time the motor speed should be about 8% FRPMMAX and be high enough to generate a detectable BEMF and allow closed loop operation to begin. The commutation position compensation has been previously discussed. The motor will continue to accelerate as long as the voltage on the RCVCO is less than the voltage on VSPEED. During this time the motor will receive full N-channel drive limited only by ILIMIT. As the voltage on RCVCO approaches that of VSPEED the CISC capacitor will charge and begin to control the gate drive to the N-channel transistor by setting a level for comparison on the 25kHz PWM saw tooth waveform generated on CPWM. The compensation of the speed loop is accomplished on CSC and on CISC which are outputs of transconductance amplifiers with a gm = 2.3 ¥ 10–4 . Figure 8. Speed Control Block Diagram. + – + – MODE SELECT ISNS RCVCO VSPEED CSC CISC 8 20 1 CPWM 6 21 5 + – 0.23mmho 0.23mmho LEVEL SHIFT +1.4V LINEAR CONTROL TO LOW-SIDE GATE DRIVE PWM CONTROL TO COMMUTATION LOGIC Figure 7. ILIMIT Output Off-Time vs. COS. Note: 100pF gives 10µs, 200pF gives 20µs, etc. 0 100 200 300 400 500 60 50 40 30 20 10 0 CIOS (pF) Slope dT C dV i V A k == = µ = 5 50 100 Ω Speed Control The speed control section of the ML4428 is detailed in Figure 8. The two transconductance amplifiers with outputs at CSC and CISC each have a gm of 0.23mmhos. The bandwidth of the current feedback component of the speed control is set at CISC as follows: f CC dB ISC ISC 3 45 23 10 2 366 10 = × π = × −− .. For f3dB = 50kHz, CISC would be 730pF. The filter components on the CSC pin set the dominant pole in the system and should have a bandwidth of about 10% of the position filter on the RCVCO pin. Typically this is in the 1 to 10Hz range. |
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