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ML4902CT Datasheet(PDF) 10 Page - Micro Linear Corporation |
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ML4902CT Datasheet(HTML) 10 Page - Micro Linear Corporation |
10 / 12 page ML4902 10 LAYOUT ISSUES The two pins of the ML4902 which actually sense the current limit voltage are ISENSE and GND. To facilitate the required low-level sensing of the voltage between these pins, there is no connection inside the ML4902 between GND and PWR GND. Because of this, there must be an external connection between the ML4902 GND and PWR GND pins. PWR GND must have a low impedance connection to the ground plane used on the board, as high instantaneous currents will flow in PWR GND when N DRV L and N DRV H switch the capacitive loads of the output MOSFET gates. At the same time, GND must not see the resulting switching spikes. If a current sensing resistor is used, the voltage across the resistor must be Kelvin-sensed. This ensures that the ML4902 monitors only the voltage across the resistor, and ignores the voltage drops and inductive transients in the PCB traces which carry current into and out of this resistor. The two pins of the ML4902 which must be Kelvin-connected to the sense resistor are ISENSE and GND. PWR GND should then return to the to the grounded end of RSENSE as well, using a high current Kelvin connection. This causes any noise across the resistor to appear primarily as a common-mode signal on ISENSE, GND, and PWR GND. Figure 4 shows a recommended implementation of these PCB layout requirements. When directly monitoring the voltage across the channel of the synchronous rectifier, the voltage across that MOSFET should be sensed as closely as possible to its drain. If a resistor divider is used to reduce the voltage at the ISENSE pin for a given current through (Q3||Q4)’s channel resistance, then the lower end of the divider should be returned to the immediate vicinity of its source. This ensures that the ML4902 monitors only the voltage across the synchronous rectifier, and not the voltage drops or inductive transients in the PCB traces which carry current into and out of it. If a PC board with a dedicated ground plane is used (recommended), the best return points for GND and PWR GND are directly into the ground plane. If the board does not have a dedicated ground plane, GND must be returned to a point near the IC which is relatively free from switching transients. Such a point may need to be empirically determined but will usually be near the ground connection of the output capacitor bank. MISCELLANEOUS POINTS ISENSE is the input to a medium-speed, high-sensitivity comparator (roughly comparable to an LM339-type comparator in terms of speed of response). Because of the leading-edge blanking on this comparator, it has a substantial ability to reject switching noise. Still, proper circuit function requires that the comparator not see significant noise at the time during which the synchronous rectifier MOSFET is on. The compensation components R4 and C13 are high- impedance nodes connected to the output of the voltage loop error amplifier. These components should be kept in close proximity to the ML4902. C13 should be returned to GND, not to PWR GND or the ground plane of the PC board. Keep the VREF bypass capacitor C8 close to the ML4902. Ensure that its ground connection is to GND, not to PWR GND. The 12V VDD input is the supply from which the internal circuitry of the ML4902 operates. VDD also provides the gate drive for N DRV H and N DRV L. The VDD bypass capacitors C10 and C20 should be returned to PWR GND or to the PC board ground plane. They should not be returned to GND due to high transient currents which could interfere with the current sensing function. VCC is the input to the 5V undervoltage lockout comparator circuitry. The 5V UVLO function makes the start-up of the ML4902 independent of power sequencing. It also provides additonal overcurrent protection in case VCC should go below acceptable levels (current drawn from the bulk 5V supply will rise as the actual voltage of that supply decreases). To reject switching noise on the 5V input, an RC filter should be used between the 5V source and VCC. Typical values for this filter are R2 = 1k Ω, and C11 = 220nf. Optional capacitor C22 may be needed in some layouts to filter out “glitches” which could occur on the PWR GOOD signal. In conjunction with the resistive pullup for the PWR GOOD line, its value should yield an RC product of approximately 5µs. In order to reduce circuit size, complexity, and cost, an all N-channel power MOSFET output stage is employed. The gate drive voltage for both the sourcing and the rectifying MOSFETs is derived from the 12V input bus. This delivers at least 10V of VGS enhancement to the rectifier MOSFET(s). The power sourcing MOSFET(s), however, have a worst-case VGS enhancement of about 6V, and must therefore be logic-level parts. If a given design uses power MOSFETs in an 8 pin SOIC package style, keep in mind that the thermal dissipation capability of these parts is largely dictated by the copper area available to their drains. A good layout will maximize this area. DESIGN CONSIDERATIONS (Continued) |
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