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ML6696 Datasheet(PDF) 3 Page - Micro Linear Corporation |
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ML6696 Datasheet(HTML) 3 Page - Micro Linear Corporation |
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3 / 16 page  ML6696 3 PIN DESCRIPTION (Pin Number in Parentheses is for PLCC Version) PIN NAME FUNCTION 1 (9) TXCLK Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of this clock. 2 (10) RXD3 Receive data TTL output. Output is valid on RXCLK’s rising edge. 3, 4, 5, (11) DGND1 Digital ground 6 (12) RXD2 Receive data TTL output. Output is valid on RXCLK’s rising edge. 7 (13) DVCC1 Digital positive power supply 8 (14) RXD1 Receive data TTL output. Output is valid on RXCLK’s rising edge. 9, 10, 11 (15) DGND2 Digital ground 12 (16) RXD0 Receive data TTL output. Output is valid on RXCLK’s rising edge. 13 (17) RXCLK Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at VIN+/-. Receive data are clocked out at RXD<3:0> on the falling edges of this clock, and should be sampled on rising edges. RXCLK is phase- aligned to CLKREF in the absence of a 100BASE-FX signal at VIN+/–. 14 (18) CRS Carrier Sense TTL output. CRS goes high in the presence of non- idle signals at VIN+/-, or when the ML6696 is transmitting. CRS goes low when there is no transmit activity and receive is idle. In repeater or full-duplex mode, CRS goes high in the presence of non- idle signals at VIN+/– only. 15 (19) COL Collision Detected TTL output. COL goes high upon detection of a collision on the network, and remains high as long as the collision condition persists. COL is low when the ML6696 operates in full-duplex, repeater, or loopback modes. PIN NAME FUNCTION 16, 17 (20) DGND3 Digital ground 18 (21) RXDV Receive data valid TTL output. This output is high when the ML6696 is receiving a data packet. RXDV is valid on RXCLK’s rising edge. 19 (22) DVCC2 Digital positive power supply 20 (23) RXER Receive error TTL output. This output goes high to indicate error or invalid symbols within a packet, or corrupted idle between packets. RXER is valid on RXCLK’s rising edge. 21 (24) MDC MII Serial Management Interface clock TTL input. A clock at this pin clocks serial data into or out of the ML6696’s MII management registers through the MDIO pin. The maximum clock frequency at MDC is 2.5MHz. 22 (25) MDIO MII Serial Management Interface data TTL input/output. Serial data are written to and read from the management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Output data is valid on MDC's rising edge 23 (26) DGND4 Digital ground 24 (27) DVCC5 Digital positive power supply 25, 26 (28) DGND5 Digital ground 27, 28 (29, 30) NC No connect 29 (31) CAPDC Data quantizer offset-correction loop, offset-storage capacitor input pin. The capacitor tied between this pin and AVCC stores the amplified data quantizer offset voltage and also sets the dominant pole in the offset-correction loop. A 0.1µF surface mount is recommended. |
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Similar Description - ML6696 |
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