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MT28C6428P20 Datasheet(PDF) 11 Page - Micron Technology |
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MT28C6428P20 Datasheet(HTML) 11 Page - Micron Technology |
11 / 48 page 11 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 ©2002, Micron Technology, Inc. 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY ADVANCE Register data is updated and latched on the falling edge of F_OE# or F_CE#, whichever occurs last. The latest falling edge of either of these two signals up- dates the latch within a given READ cycle. Latching the data prevents errors from occurring if the register input changes during a status register read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 8 defines the sta- tus register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0–DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 3. The 8-bit command code is input to the device on DQ0–DQ7 (see Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PRO- GRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSMS bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PRO- GRAM operation only when F_VPP is within its correct voltage range. Table 4 Command Definitions FIRST BUS CYCLE SECOND BUS CYCLE COMMAND OPERATION ADDRESS1 DATA OPERATION ADDRESS1 DATA1 READ ARRAY WRITE WA FFh READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ IA ID READ STATUS REGISTER WRITE BA 70h READ X SRD CLEAR STATUS REGISTER WRITE BA 50h READ QUERY WRITE QA 98h READ QA QD BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h PROGRAM SETUP WRITE WA 40h WRITE WA WD ACCELERATED PROGRAMMING ALGORITHM (APA) WRITE WA 10h WRITE WA WD PROGRAM/ERASE SUSPEND WRITE BA B0h PROGRAM/ERASE RESUME – ERASE CONFIRM WRITE BA D0h LOCK BLOCK WRITE BA 60h WRITE BA 01h UNLOCK BLOCK WRITE BA 60h WRITE BA D0h LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh CHECK BLOCK ERASE WRITE BA 20h WRITE BA D1h PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh ENABLE/DISABLE DEEP POWER-DOWN WRITE DPW 60h WRITE DPW 03h NOTE: 1. BA: Address within the block DPW: BBCFh = Disable deep power-down BBDFh = Enable deep power-down IA: Identification code address ID: Identification code data LPA: Lock protection register address PA: Protection register address PD: Data to be written at location PA QA: Query code address QD: Query code data SRD: Data read from the status register WA: Word address of memory location to be written, or read WD: Data to be written at the location WA X: “Don’t Care” |
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