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MT28F004B3SG-8T Datasheet(PDF) 9 Page - Micron Technology |
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MT28F004B3SG-8T Datasheet(HTML) 9 Page - Micron Technology |
9 / 30 page 9 4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc. 4Mb SMART 3 BOOT BLOCK FLASH MEMORY latched on the falling edge of OE# or CE#, whichever occurs last. If the contents of the status register change during a READ of the status register, either OE# or CE# may be toggled while the other is held LOW to update the output. Following a WRITE or ERASE, the device automati- cally enters the status register read mode. In addition, a READ during a WRITE or ERASE produces the status register contents on DQ0–DQ7. When the device is in the erase suspend mode, a READ operation produces the status register contents until another command is is- sued. In certain other modes, READ STATUS REGIS- TER may be given to return to the status register read mode. All commands and their operations are described in the Command Set and Command Execution sections. IDENTIFICATION REGISTER A READ of the two 8-bit device identification registers requires the same input sequencing as a READ of the array. WE# must be HIGH, and OE# and CE# must be LOW. However, ID register data is output only on DQ0– DQ7, regardless of the condition of BYTE# on the MT28F400B3. A0 is used to decode between the two bytes of the device ID register; all other address inputs are “Don’t Care.” When A0 is LOW, the manufacturer com- patibility ID is output, and when A0 is HIGH, the device ID is output. DQ8–DQ15 are High-Z when BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are 00h when the manufacturer compatibility ID is read and 44h when the device ID is read. To get to the identification register read mode, READ IDENTIFICATION may be issued while the device is in certain other modes. In addition, the identification regis- ter read mode can be reached by applying a super-volt- age (VID) to the A9 pin. Using this method, the ID register can be read while the device is in any mode. When A9 is returned to VIL or VIH, the device returns to the previous mode. INPUT OPERATIONS The DQ pins are used either to input data to the array or to input a command to the CEL. A command input issues an 8-bit command to the CEL to control the mode of operation of the device. A WRITE is used to input data to the memory array. The following section describes both types of inputs. More information describing how to use the two types of inputs to write or erase the device is provided in the Command Execution section. COMMANDS To perform a command input, OE# must be HIGH, and CE# and WE# must be LOW. Addresses are “Don’t Care” but must be held stable, except during an ERASE CONFIRM (described in a later section). The 8-bit com- PARAMETER BLOCKS The two 8KB parameter blocks store less sensitive and more frequently changing system parameters and also may store configuration or diagnostic coding. These blocks are enabled for erasure when the VPP pin is at VPPH. No super-voltage unlock or WP# control is required. MAIN MEMORY BLOCKS The four remaining blocks are general-purpose memory blocks and do not require a super-voltage on RP# or WP# control to be erased or written. These blocks are intended for code storage, ROM-resident applica- tions or operating systems that require in-system update capability. OUTPUT (READ) OPERATIONS The MT28F004B3 and MT28F400B3 feature three dif- ferent types of READs. Depending on the current mode of the device, a READ operation produces data from the memory array, status register or device identification register. In each of these three cases, the WE#, CE# and OE# inputs are controlled in a similar manner. Moving between modes to perform a specific READ is described in the Command Execution section. MEMORY ARRAY To read the memory array, WE# must be HIGH, and OE# and CE# must be LOW. Valid data is output on the DQ pins when these conditions have been met and a valid address is given. Valid data remains on the DQ pins until the address changes, or until OE# or CE# goes HIGH, whichever occurs first. The DQ pins continue to output new data after each address transition as long as OE# and CE# remain LOW. The MT28F400B3 features selectable bus widths. When the memory array is accessed as a 256K x 16, BYTE# is HIGH, and data is output on DQ0–DQ15. To access the memory array as a 512K x 8, BYTE# must be LOW, DQ8– DQ14 must be High-Z, and all data must be output on DQ0–DQ7. The DQ15/A-1 pin becomes the lowest or- der address input so that 524,288 locations can be read. After power-up or RESET, the device is automatically in the array read mode. All commands and their opera- tions are described in the Command Set and Command Execution sections. STATUS REGISTER Performing a READ of the status register requires the same input sequencing as a READ of the array except that the address inputs are “Don’t Care.” The status register contents are always output on DQ0–DQ7, regardless of the condition of BYTE# on the MT28F400B3. DQ8–DQ15 are LOW when BYTE# is HIGH, and DQ8–DQ14 are High- Z when BYTE# is LOW. Data from the status register is |
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