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MT28F800B3VG-9T Datasheet(PDF) 8 Page - Micron Technology |
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MT28F800B3VG-9T Datasheet(HTML) 8 Page - Micron Technology |
8 / 30 page 8 8Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. Q10_3.p65 – Rev. 3, Pub. 10/01 ©2001, Micron Technology, Inc. 8Mb SMART 3 BOOT BLOCK FLASH MEMORY Figure 1 Memory Address Maps Top Boot MT28F008B3/800B3xx-xxT Bottom Boot MT28F008B3/800B3xx-xxB while the ISM is active. However, there are restrictions on what commands are allowed in this condition. See the Command Execution section for more detail. DEEP POWER-DOWN MODE To allow for maximum power conservation, the MT28F800B3 and MT28F008B3 feature a very low cur- rent, deep power-down mode. To enter this mode, the RP# pin is taken to VSS ±0.2V. In this mode, the current draw is a maximum of 8µA at 3.3V VCC. Entering deep power-down also clears the status register and sets the ISM to the read array mode. MEMORY ARCHITECTURE The MT28F800B3 and MT28F008B3 memory array architecture is designed to allow sections to be erased without disturbing the rest of the array. The array is divided into eleven addressable blocks that vary in size and are independently erasable. When blocks rather than the entire array are erased, total device endurance is enhanced, as is system flexibility. Only the ERASE func- tion is block-oriented. All READ and WRITE operations are done on a random-access basis. The boot block is protected from unintentional ERASE or WRITE with a hardware protection circuit which re- quires that a super-voltage be applied to RP# or that the WP# pin be driven HIGH before erasure is commenced. The boot block is intended for the core firmware required for basic system functionality. The remaining ten blocks do not require that either of these two conditions be met before WRITE or ERASE operations. BOOT BLOCK The hardware-protected boot block provides extra security for the most sensitive portions of the firmware. This 16KB block may only be erased or written when the RP# pin is at the specified boot block unlock voltage (VHH) of 12V or when the WP# pin is HIGH. During a WRITE or ERASE of the boot block, the RP# pin must be held at VHH or the WP# pin held HIGH until the WRITE or ERASE is completed. (The WP# pin does not apply to the SOP package.) The VPP pin must be at VPPH (3.3V or 5V) when the boot block is written to or erased. FFFFFh FC000h FBFFFh FA000h F9FFFh F8000h F7FFFh E0000h DFFFFh C0000h BFFFFh A0000h 9FFFFh 80000h 7FFFFh 60000h 5FFFFh 40000h 3FFFFh 20000h 1FFFFh 00000h 16KB Boot Block 8KB Parameter Block 8KB Parameter Block 96KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block BYTE ADDRESS 7FFFFh 7E000h 7DFFFh 7D000h 7CFFFh 7C000h 7BFFFh 70000h 6FFFFh 60000h 5FFFFh 50000h 4FFFFh 40000h 3FFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h 0FFFFh 00000h WORD ADDRESS 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block 96KB Main Block 8KB Parameter Block 8KB Parameter Block 16KB Boot Block BYTE ADDRESS FFFFFh E0000h DFFFFh C0000h BFFFFh A0000h 9FFFFh 80000h 7FFFFh 60000h 5FFFFh 40000h 3FFFFh 20000h 1FFFFh 08000h 07FFFh 06000h 05FFFh 04000h 03FFFh 00000h 7FFFFh 70000h 6FFFFh 60000h 5FFFFh 50000h 4FFFFh 40000h 3FFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h 0FFFFh 04000h 03FFFh 03000h 02FFFh 02000h 01FFFh 00000h WORD ADDRESS |
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