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MT48LC64M8A2 Datasheet(PDF) 1 Page - Micron Technology |
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MT48LC64M8A2 Datasheet(HTML) 1 Page - Micron Technology |
1 / 55 page ADVANCE‡ ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. 1 512Mb: x4, x8, x16 SDRAM 512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. KEY TIMING PARAMETERS SPEED CLOCK ACCESS TIME SETUP HOLD GRADE FREQUENCY CL = 2* CL = 3* TIME TIME -7E 143 MHz – 5.4ns 1.5ns 0.8ns -75 133 MHz – 5.4ns 1.5ns 0.8ns -7E 133 MHz 5.4ns – 1.5ns 0.8ns -75 100 MHz 6ns – 1.5ns 0.8ns 128 Meg x 4 64 Meg x 8 32 Meg x 16 Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh Count 8K 8K 8K Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 4K (A0–A9, A11, A12) 2K (A0–A9, A11) 1K (A0–A9) SYNCHRONOUS DRAM MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds Pin Assignment (Top View) 54-Pin TSOP FEATURES • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply OPTIONS MARKING • Configurations 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 • WRITE Recovery (tWR) tWR = “2 CLK”1 A2 • Plastic Package – OCPL2 54-pin TSOP II (400 mil) TG • Timing (Cycle Time) 7.5ns @ CL = 2 (PC133) -7E 7.5ns @ CL = 3 (PC133) -75 • Self Refresh Standard None Low power L • Operating Temperature Commercial (0oC to +70oC) None NOTE: 1. Refer to Micron Technical Note TN-48-05. 2. Off-center parting line. Part Number Example: MT48LC32M16A2TG-75 NOTE: The # symbol indicates signal is active LOW. A dash (–) indicates x8 and x4 pin function is same as x16 pin function. VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 VDDQ DQ5 DQ6 VssQ DQ7 VDD DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VDDQ DQ12 DQ11 VssQ DQ10 DQ9 VDDQ DQ8 Vss NC DQMH CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss x8 x16 x16 x8 x4 x4 - DQ0 - NC DQ1 - NC DQ2 - NC DQ3 - NC - NC - - - - - - - - - - - - - NC - NC DQ0 - NC NC - NC DQ1 - NC - NC - - - - - - - - - - - - - DQ7 - NC DQ6 - NC DQ5 - NC DQ4 - NC - - DQM - - - - - - - - - - - - NC - NC DQ3 - NC NC - NC DQ2 - NC - - DQM - - - - - - - - - - - *CL = CAS (READ) latency 512Mb SDRAM PART NUMBERS PART NUMBER ARCHITECTURE MT48LC128M4A2TG 128 Meg x 4 MT48LC64M8A2TG 64 Meg x 8 MT48LC32M16A2TG 32 Meg x 16 |
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