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MT48LC32M16A2 Datasheet(PDF) 11 Page - Micron Technology |
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MT48LC32M16A2 Datasheet(HTML) 11 Page - Micron Technology |
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11 / 55 page  11 512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Note: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES COMMAND INHIBIT (NOP) H XXXX X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3 READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4 WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 4 BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7 (Enter self refresh mode) LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable –––– L – Active 8 Write Inhibit/Output High-Z –––– H – High-Z 8 following the Operation section; these tables provide current state/next state information. COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW. 3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active. 4. A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). |
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