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AR0230CSSC12SUEA0-DR Datasheet(PDF) 11 Page - ON Semiconductor |
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AR0230CSSC12SUEA0-DR Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 36 page AR0230CS/D Rev. 8, Pub. 11/15 EN 11 ©Semiconductor Components Industries, LLC, 2015. AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Table 3: Pin Descriptions, 80-ball iBGA Name iBGA Pin Type Description SLVS0_P A2 Output HiSPi serial data, lane 0, differential P. SLVS1_P A3 Output HiSPi serial data, lane 1, differential P. SLVSC_P A4 Output HiSPi serial DDR clock differential P. SLVS2_P A5 Output HiSPi serial data, lane 2, differential P. SLVS3_P A6 Output HiSPi serial data, lane 3, differential P. VDD_PLL B1 Power PLL power. SLVS0_N B2 Output HiSPi serial data, lane 0, differential N. SLVS1_N B3 Output HiSPi serial data, lane 1, differential N. SLVSC_N B4 Output HiSPi serial DDR clock differential N. SLVS2_N B5 Output HiSPi serial data, lane 2, differential N. SLVS3_N B6 Output HiSPi serial data, lane 3, differential N. SHUTTER B9 Output Control for external mechanical shutter. Can be left floating if not used. VAA C1, G1, D9, F9 Power Analog power. AGND C2, G2, D8, E8, F8 Power Analog ground. VDD_SLVS C4 Power 0.3V-0.6V or 1.7V - 1.9V port to HiSPi Output Driver. Set the High_VCM (R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 – 1.9V. VDD C5, J5, A9, H9, A7, D1, F1 Power Digital power. Reserved C9, F7 DGND B7, C7, D7, E7, G7, B8, C8, G8, D2, E2, F2, H2, C3, G3, H3, C6, J6 Power Digital ground. EXTCLK D3 Input External input clock. PIXCLK D4 Output Pixel clock out. Dout is valid on rising edge of this clock. SADDR D5 Input Two-Wire Serial address select. 0: 0x20. 1: 0x30 TRIGGER D6 Input Exposure synchronization input. VAA_PIX E9 Power Pixel power. VDD_IO E1, H1, J2, J7, A8, G9, J9 Power I/O supply power. SDATA E3 I/O Two-Wire Serial data I/O. FLASH E4 Output Flash control output. FRAME_VALID E5 Output Asserted when Dout frame data is valid. SCLK E6 Input Two-Wire Serial clock input. DOUT11 F3 Output Parallel pixel data output (MSB) DOUT10 F4 Output Parallel pixel data output. DOUT9F5 Output Parallel pixel data output. LINE_VALID F6 Output Asserted when Dout line data is valid. DOUT8G4 Output Parallel pixel data output. DOUT7G5 Output Parallel pixel data output. DOUT6G6 Output Parallel pixel data output. DOUT5H4 Output Parallel pixel data output. DOUT4H5 Output Parallel pixel data output. DOUT3H6 Output Parallel pixel data output. RESET_BAR H7 Input Asynchronous reset (active LOW). All settings are restored to factory default. |
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