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AR0330CM1C12SHKA0-CP Datasheet(PDF) 8 Page - ON Semiconductor |
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AR0330CM1C12SHKA0-CP Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 77 page AR0330_DS Rev. U Pub. 4/15 EN 8 ©Semiconductor Components Industries, LLC,2015. AR0330: 1/3-Inch CMOS Digital Image Sensor Working Modes Figure 2: Typical Configuration: Serial Four-Lane HiSPi Interface Notes: 1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0F and 0.1F decoupling capacitors for every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may vary depending on layout and design considerations. 2. To allow for space constraints, ON Semiconductor recommends having 0.1F decoupling capacitor inside the module as close to the pads as possible. In addition, place a 10F capacitor for each sup- ply off-module but close to each supply. 3. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 4. The pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. TEST pin should be tied to DGND. 7. Set High_VCM (R0x306E[9]) to 0 (default) to use the VDD_HiSPi_TX in the range of 0.4 – 0.8V. Set High_VCM to 1 to use a range of 1.7 – 1.9V. 8. The package pins or die pads used for the MIPI data and clock as well as the parallel interface must be left floating. 9. The VDD_MIPI package pin and sensor die pad should be connected to a 2.8V supply as VDD_MIPI is tied to the VDD_PLL supply both in the package routing and also within the sensor die itself. 10. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating. 11. If the TRIGGER or OE_BAR pins or pads are not used, then they should be tied to DGND. 12. The GND_SLVS pad must be tied to DGND. It is connected this way in the CLCC and CSP packages. VDD_IO VDD_HiSPi VDD_PLL VDD VAA VDD VAA VAA_PIX Master clock (6–27 MHz) SCLK SDATA RESET_BAR TEST EXTCLK DGND GND_SLVS AGND Digital ground Analog ground Digital Core power1 HiSPi power1 Analog power1 To controller From controller VDD_IO PLL power1 Digital I/O power1 Analog power1 VAA_PIX SLVSC_N SLVSC_P SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_N SLVS3_P SLVS3_N SADDR FLASH SHUTTER 1.o μF 1.o μF 1.o μF 1.o μF 1.o μF 1.o μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF OE_BAR TRIGGER (HiSPi-serial interface) VDD_HiSPi_TX 1.o μF 0.1μF SLVS2_P |
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