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AR0331SRSC00XUEE0-DRBR1 Datasheet(PDF) 9 Page - ON Semiconductor |
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AR0331SRSC00XUEE0-DRBR1 Datasheet(HTML) 9 Page - ON Semiconductor |
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9 / 72 page  AR0331_DS Rev. L Pub. 5/15 EN 8 ©Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview out and design considerations. Refer to the AR0331 demo headboard schematics for circuit recom- mendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. Figure 3: Typical Configuration: Parallel Pixel Data Interface Notes: 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output inter- face is used. 4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Refer to the AR0331 demo headboard schematics for circuit recom- mendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 7. The EXTCLK input is limited to 6-48 MHz. VDD Master clock (6-48 MHz) SDATA SCLK TEST FRAME_VALID DOUT [11:0] EXTCLK DGND Digital ground Analog ground Digital core power1 To controller From Controller LINE_VALID PIXCLK RESET_BAR VDD_IO Digital I/O power1 VAA VAA_PIX Analog power1 VDD_PLL PLL power1 Analog power1 VAA_PIX VDD_IO VDD_PLL VDD VAA TRIGGER OE_BAR AGND SADDR SHUTTER FLASH |
Similar Part No. - AR0331SRSC00XUEE0-DRBR1 |
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Similar Description - AR0331SRSC00XUEE0-DRBR1 |
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