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AR0134CSSM25SUEA0-DRBR Datasheet(PDF) 10 Page - ON Semiconductor |
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AR0134CSSM25SUEA0-DRBR Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 41 page AR0134_DS Rev. G Pub. 6/15 EN 10 ©Semiconductor Components Industries, LLC,2015. AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor Configuration and Pinout Configuration and Pinout The figures and tables below show a typical configuration for the AR0134 image sensor and show the package pinouts. Figure 4: Typical Configuration: Serial Four-Lane HiSPi Interface Notes: 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The parallel interface output pads can be left unconnected if the serial output interface is used. 5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Refer to the AR0134 demo headboard schematics for circuit recom- mendations. 6. ON Semiconductor recommends that analog power planes be placed in a manner such that cou- pling with the digital power planes is minimized. 7. Although 4 serial lanes are shown, the AR0134 supports only 2 or 3 lane HiSPi. VDD_IO VDD_SLVS VDD_PLL VDD VAA VDD VAA VAA_PIX Master clock (6–50 MHz) SDATA SCLK RESET_BAR TEST EXTCLK DGND AGND Digital ground Analog ground Digital Core power1 HiSPi power1 Analog power1 To controller From controller VDD_IO VDD_PLL PLL power1 Digital I/O power1 Analog power1 VAA_PIX SLVSC_N SLVSC_P SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_P SLVS2_N SLVS3_P7 SLVS3_N7 FLASH OE_BAR STANDBY |
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