© Semiconductor Components Industries, LLC, 2012

October, 2012 − Rev. 0

1

Publication Order Number:

CAV25128/D

CAV25128

128-Kb SPI Serial CMOS

EEPROM

Description

The CAV25128 is a 128−Kb Serial CMOS EEPROM device

internally organized as 16Kx8 bits. This features a 64−byte page write

buffer and supports the Serial Peripheral Interface (SPI) protocol. The

device is enabled through a Chip Select (CS) input. In addition, the

required bus signals are clock input (SCK), data input (SI) and data

output (SO) lines. The HOLD input may be used to pause any serial

communication with the CAV25128 device. The device features

software and hardware write protection, including partial as well as

full array protection.

On−Chip ECC (Error Correction Code) makes the device suitable

for high reliability applications.

Features

− Protect 1/4, 1/2 or Entire EEPROM Array

Compliant

SI

SO

CAV25128

SCK

CS

WP

HOLD

Figure 1. Functional Symbol

http://onsemi.com

PIN CONFIGURATION

See detailed ordering and shipping information in the package

dimensions section on page 13 of this data sheet.

ORDERING INFORMATION

SOIC−8

V SUFFIX

CASE 751BD

SOIC (V), TSSOP (Y)

TSSOP−8

Y SUFFIX

CASE 948AL

Chip Select

CS

Serial Data Output

SO

Write Protect

WP

Ground

Serial Data Input

SI

Serial Clock

SCK

Function

Pin Name

PIN FUNCTION

Hold Transmission Input

HOLD

Power Supply

SI

HOLD

WP

SO

CS

1

SCK