CAV25010, CAV25020, CAV25040

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4

Pin Description

SI: The serial data input pin accepts op−codes, addresses

and data. In SPI modes (0,0) and (1,1) input data is latched

on the rising edge of the SCK clock input.

SO: The serial data output pin is used to transfer data out of

the device. In SPI modes (0,0) and (1,1) data is shifted out

on the falling edge of the SCK clock.

SCK: The serial clock input pin accepts the clock provided

by the host and used for synchronizing communication

between host and CAV25010/20/40.

CS: The chip select input pin is used to enable/disable the

CAV25010/20/40. When CS is high, the SO output is

tri−stated (high impedance) and the device is in Standby

Mode (unless an internal write operation is in progress).

Every

communication

session

between

host

and

CAV25010/20/40 must be preceded by a high to low

transition and concluded with a low to high transition of the

CS input.

WP: The write protect input pin will allow all write

operations to the device when held high. When WP pin is

tied low all write operations are inhibited.

HOLD: The HOLD input pin is used to pause transmission

between host and CAV25010/20/40, without having to

retransmit the entire sequence at a later time. To pause,

HOLD must be taken low and to resume it must be taken

back high, with the SCK input low during both transitions.

When not used for pausing, the HOLD input should be tied

Functional Description

The CAV25010/20/40 devices support the Serial

Peripheral Interface (SPI) bus protocol, modes (0,0) and

(1,1). The device contains an 8−bit instruction register. The

instruction set and associated op−codes are listed in Table 7.

Reading data stored in the CAV25010/20/40 is

accomplished by simply providing the READ command and

an address. Writing to the CAV25010/20/40, in addition to

a WRITE command, address and data, also requires

enabling the device for writing by first setting certain bits in

a Status Register, as will be explained later.

After a high to low transition on the CS input pin, the

CAV25010/20/40 will accept any one of the six instruction

op−codes listed in Table 7 and will ignore all other possible

8−bit combinations. The communication protocol follows

the timing from Figure 2.

Instruction

Opcode

Operation

WREN

0000 0110

Enable Write Operations

WRDI

0000 0100

Disable Write Operations

RDSR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register

READ

0000 X011

Read Data from Memory

WRITE

0000 X010

Write Data to Memory

9. X = 0 for CAV25010, CAV25020. X = A8 for CAV25040

Figure 2. Synchronous Data Timing

CS

SCK

SI

SO

HI−Z

VALID

IN

VALID

OUT

HI−Z

Status Register

The Status Register, as shown in Table 8, contains a

number of status and control bits.

The RDY (Ready) bit indicates whether the device is busy

with a write operation. This bit is automatically set to 1 during

an internal write cycle, and reset to 0 when the device is ready

to accept commands. For the host, this bit is read only.

The WEL (Write Enable Latch) bit is set/reset by the

WREN/WRDI commands. When set to 1, the device is in a

Write Enable state and when set to 0, the device is in a Write

Disable state.

The BP0 and BP1 (Block Protect) bits determine which

blocks are currently write protected. They are set by the user

with the WRSR command and are non−volatile. The user is

allowed to protect a quarter, one half or the entire memory,

by setting these bits according to Table 9. The protected

blocks then become read−only.