CM1215

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5

APPLICATION INFORMATION

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic

series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically

a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking

an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on

the line being protected is:

where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be

increment in VCL!

increased negative voltage on the line being protected.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.

Figure 3. Application of Positive ESD Pulse between Input Channel and Ground

POSITIVE SUPPLY

PATH OF ESD CURRENT

PULSE (IESD)

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

CHANNEL

IMPUT

LINE BEING

PROTECTED

ONE

CHANNEL

D1

D2

C1

L1

GROUND RAIL

CHASSI‘S GROUND