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MT28F322D20FH-80BET Datasheet(PDF) 1 Page - Micron Technology |
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MT28F322D20FH-80BET Datasheet(HTML) 1 Page - Micron Technology |
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1 / 44 page  1 2 Meg x 16 Async/Page/Burst Flash Memory ©2002, Micron Technology, Inc. MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. FLASH MEMORY MT28F322D20 MT28F322D18 Low Voltage, Extended Temperature 0.18µm Process Technology BALL ASSIGNMENT 58-Ball FBGA FEATURES • Flexible dual-bank architecture – Support for true concurrent operation with zero latency – Read bank a during program bank b and vice versa – Read bank a during erase bank b and vice versa • Basic configuration: Seventy-one erasable blocks – Bank a (8Mb for data storage) – Bank b (24Mb for program storage) •VCC, VCCQ, VPP voltages – 1.70V (MIN), 1.90V (MAX) VCC, VCCQ (MT28F322D18 only) – 1.80V VCC, VCCQ (MIN); 2.20V VCC (MAX)and 2.25V VCCQ (MAX) (MT28F322D20 only) – 0.9V (TYP) VPP (in-system PROGRAM/ERASE) – 12V ±5% (HV) VPP tolerant (factory programming compatibility) • Random access time: 70ns/80ns @ 1.70V VCC • Burst Mode read access (MT28F322D20) – MAX clock rate: 54 MHz (tCLK = 18.5ns) – Burst latency: 70ns @ 1.80V VCC and 54 MHz – tACLK: 17ns @ 1.80V VCC and 54 MHz • Page Mode read access1 – Eight-word page – Interpage read access: 70ns/80ns @ 1.80V – Intrapage read access: 30ns @ 1.80V • Low power consumption (VCC = 2.20V) – Asynchronous READ < 15mA (MAX) – Standby < 50µA – Automatic power saving feature (APS) • Enhanced write and erase suspend options – ERASE-SUSPEND-to-READ within same bank – PROGRAM-SUSPEND-to-READ within same bank – ERASE-SUSPEND-to-PROGRAM within same bank • Dual 64-bit chip protection registers for security purposes • Cross-compatible command support – Extended command set – Common flash interface • PROGRAM/ERASE cycle – 100,000 WRITE/ERASE cycles per block NOTE: 1. Data based on MT28F322D20 device. 2. A “5” in the part mark represents two different frequencies: 54 MHz (MT28F322D20) or 52 MHz (MT28F322D18) A B C D E F G 1 2 3 4 5 6 7 8 Top View (Ball Down) A11 A12 A13 A15 VCCQ VSS DQ7 A18 A17 A19 WP# DQ1 DQ9 VCCQ VPP RST# WE# DQ12 DQ2 DQ10 DQ3 VSS A20 WAIT# DQ6 DQ13 DQ5 A4 A3 A2 A1 A0 OE# VSSQ A6 A5 A7 CE# DQ0 DQ8 A8 A9 A10 A14 DQ15 DQ14 VSSQ VCC CLK ADV# A16 DQ4 DQ11 VCC NOTE: See page 7 for Ball Description Table. See page 43 for mechanical drawing. OPTIONS MARKING • Timing 70ns access -70 80ns access -80 • Frequency 54 MHz 52 40 MHz 4 No burst operation None • Boot Block Configuration Top T Bottom B • Package 58-ball FBGA (8 x 7 ball grid) FH • Operating Temperature Range Extended (-40ºC to +85ºC) ET Part Number Example: MT28F322D20FH-804 BET |
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