 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MT48LC2M8A1 Datasheet(PDF) 1 Page - Micron Technology |
|
||||||||||||||||||||||||||||||
MT48LC2M8A1 Datasheet(HTML) 1 Page - Micron Technology |
|
|
1 / 50 page  PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 1 16 Meg: x4, x8 SDRAM ©1998, Micron Technology, Inc. 16MSDRAMx4x8_B.p65 – Rev. 5/98 16 MEG: x4, x8 SDRAM 16Mb (x4/x8) SDRAM PART NUMBERS PART NUMBER ARCHITECTURE MT48LC4M4A1TG S 4 Meg x 4 (tWR = 1 CLK) MT48LC2M8A1TG S 2 Meg x 8 (tWR = 1 CLK) 4 MEG x 4 2 MEG x 8 Configuration 2 Meg x 4 x 2 banks 1 Meg x 8 x 2 banks Refresh Count 4K 4K Row Addressing 2K (A0-A10) 2K (A0-A10) Bank Addressing 2 (BA) 1 (BA) Column Addressing 1K (A0-A9) 512 (A0-A8) FEATURES • PC100-compliant; includes CONCURRENT AUTO PRECHARGE • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply • Longer lead TSOP for improved reliability (OCPL*) • One- and two-clock WRITE recovery (tWR) versions OPTIONS MARKING • Configurations 4 Meg x 4 (2 Meg x 4 x 2 banks) 4M4 2 Meg x 8 (1 Meg x 8 x 2 banks) 2M8 • WRITE Recovery (tWR/tDPL) tWR = 1 CLK A1 tWR = 2 CLK (Contact factory for availability.)A2 • Plastic Package - OCPL* 44-pin TSOP (400 mil) TG • Timing (Cycle Time) 8ns; tAC = 6ns @ CL = 3 -8B 10ns; tAC = 9ns @ CL = 2 -10 NOTE: The 16Mb SDRAM base number differentiates the offerings in two places: MT48LC2M8A1 S. The fourth field distinguishes the architecture offering: 4M4 designates 4 Meg x 4, and 2M8 designates 2 Meg x 8. The fifth field distinguishes the WRITE recovery offering: A1 designates one CLK and A2 designates two CLKs. Part Number Example: MT48LC2M8A1TG-10 S PIN ASSIGNMENT (Top View) 44-Pin TSOP VDD DQ0 VssQ DQ1 VDDQ DQ2 VssQ DQ3 VDDQ NC NC WE# CAS# RAS# CS# BA A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Vss DQ7 VssQ DQ6 VDDQ DQ5 VssQ DQ4 VDDQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss - NC - DQ0 - NC - DQ1 - - - - - - - - - - - - - - - NC - DQ3 - NC - DQ2 - - - - - - - - - - - - - - x4 x8 x8 x4 NOTE: The # symbol indicates signal is active LOW. A dash (-) indicates x4 pin function is same as x8 pin function. SYNCHRONOUS DRAM MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets. KEY TIMING PARAMETERS SPEED CLOCK ACCESS TIME SETUP HOLD GRADE FREQUENCY CL = 2** CL = 3** TIME TIME -8B 125 MHz – 6ns 2ns 1ns -10 100 MHz – 7.5ns 3ns 1ns -8B 83 MHz 9ns – 2ns 1ns -10 66 MHz 9ns – 3ns 1ns * Off-center parting line **CL = CAS (READ) latency |
Similar Part No. - MT48LC2M8A1 |
|
Similar Description - MT48LC2M8A1 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
