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MT28F128J3FS-11ET Datasheet(PDF) 9 Page - Micron Technology |
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MT28F128J3FS-11ET Datasheet(HTML) 9 Page - Micron Technology |
9 / 52 page 9 128Mb, 64Mb, 32Mb Q-Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ©2002, Micron Technology, Inc. 128Mb, 64Mb, 32Mb Q-FLASH MEMORY valid; the data may be partially corrupted after a pro- gram or partially changed after an erase or lock bit configuration. After RP# goes to logic HIGH (VIH), and after tRS, another command can be written. It is important to assert RP# during system reset. After coming out of reset, the system expects to read from the Flash memory. During block erase, program, or lock bit configuration mode, automated Flash memo- ries provide status information when accessed. When a CPU reset occurs with no Flash memory reset, proper initialization may not occur because the Flash memory may be providing status information instead of array data. Micron Flash memories allow proper initializa- tion following a system reset through the use of the RP# input. RP# should be controlled by the same RESET# signal that resets the system CPU. READ QUERY The READ QUERY operation produces block status information, CFI ID string, system interface informa- tion, device geometry information, and extended query information. READ IDENTIFIER CODES The READ IDENTIFIER CODES operation produces the manufacturer code, device code, and the block lock configuration codes for each block (see Figure 2). The block lock configuration codes identify locked and un- locked blocks. WRITE Writing commands to the CEL allows reading of de- vice data, query, identifier codes, and reading and clear- ing of the status register. In addition, when VPEN = VPENH, block erasure, program, and lock bit configuration can also be performed. The BLOCK ERASE command requires suitable com- mand data and an address within the block. The BYTE/ WORD PROGRAM command requires the command and address of the location to be written to. The CLEAR BLOCK LOCK BITS command requires the command and any address within the device. SET BLOCK LOCK BITS command requires the command and the block to be locked. The CEL does not occupy an addressable memory location. It is written to when the device is enabled and WE# is LOW. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CEx that disables the device (see Table 2). Standard microprocessor write timings are used. Reserved for Future Implementation Manufacturer Code Device Code 010000h 00FFFFh 000004h 000003h 000002h 000001h 000000h Reserved for Future Implementation Reserved for Future Implementation Reserved for Future Implementation Block 63 Block 0 3FFFFFh 3F0003h 3F0002h 3F0000h 3EFFFFh 1EFFFFh 1F0003h 1F0002h 1F0000h 01FFFFh 010003h 010002h Block 63 Lock Configuration Block 0 Lock Configuration Reserved for Future Implementation (Blocks 32 through 62) Reserved for Future Implementation 7FFFFFh 7F0003h 7F0002h 7F0000h 7EFFFFh Block 127 Lock Configuration Reserved for Future Implementation Block 31 Reserved for Future Implementation (Blocks 2 through 30) Block 1 Reserved for Future Implementation Block 1 Lock Configuration Block 127 Block 31 Lock Configuration (Blocks 64 through 126) Figure 2 Device Identifier Code Memory Map NOTE: When obtaining these identifier codes, A0 is not used in either x8 or x16 modes. Data is always given on the LOW byte in x16 mode (upper byte contains 00h). |
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