9

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 – Rev. B; Pub 3/01

©2001, Micron Technology, Inc.

1 MEG x 16

FPM DRAM

NOTES

1.

2.

f = 1 MHz.

3.

values are obtained with minimum cycle time

and the output open.

4.

Enables on-chip refresh and address counters.

5.

The minimum specifications are used only to

indicate cycle time at which proper operation

over the full temperature range (0°C

≤ T

for commercial and (-20°C

≤ T

extended “ET” is ensured.

6.

An initial pause of 100µs is required after power-

up, followed by eight RAS# refresh cycles (RAS#-

ONLY or CBR), before proper device operation is

ensured. The eight RAS# cycle wake-ups should

ment is exceeded.

7.

8.

measuring timing of input signals. Transition

9.

In addition to meeting the transition rate

specification, all input signals must transit

monotonic manner.

the last valid READ cycle.

12. Measured with a load equivalent to two TTL

13. If CAS# is LOW at the falling edge of RAS#, Q will

be maintained from the previous cycle. To

initiate a new cycle and clear the Q buffer, CAS#

(MAX) was specified as a reference point only. If

limit, then access time was controlled exclusively

always be met.

(MAX) was specified as a reference point only. If

limit, then access time was controlled exclusively

cycle.

achieves the open circuit condition; it is not a

operating parameters in LATE WRITE and READ-

(MIN), the cycle is an EARLY WRITE cycle and the

data out-put will remain an open circuit through-

the cycle is a READ WRITE and the data output

will contain data read from the selected cell. If

neither of the above conditions is met, the state

of Q (at access time and until CAS# or OE# goes

WE# taken LOW after CAS# goes LOW result in a

LATE WRITE (OE#-controlled) cycle.

19. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. During a READ cycle, if OE# is LOW then taken

HIGH before CAS# goes HIGH, Q goes open. If

OE# is tied permanently LOW, LATE WRITE and

READ-MODIFY-WRITE operations are not

permissible and should not be attempted.

21. A HIDDEN REFRESH may also be performed

after a WRITE cycle. In this case, WE# = LOW and

OE# = HIGH.

23. Column address changed once each cycle.

24. LATE WRITE and READ-MODIFY-WRITE cycles

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE

cycle. The DQs will provide the previously read

data if CAS# remains LOW and OE# is taken back

to OE# going back LOW, the DQs will remain

open.

26. The 3ns minimum is a parameter guaranteed by

design.

27. The first CASx edge to transition LOW.

28. The last CASx edge to transition HIGH.

29. Output parameter (DQx) is referenced to

corresponding CAS# input; DQ0-DQ7 by CASL#

and DQ8-DQ15 by CASH#.

30. Last falling CASx edge to first rising CASx edge.

31. Last rising CASx edge to next cycle’s last rising

CASx edge.