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MT4LC4M16R6-1 Datasheet(PDF) 1 Page - Micron Technology

Part # MT4LC4M16R6-1
Description  DRAM
Download  24 Pages
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT4LC4M16R6-1 Datasheet(HTML) 1 Page - Micron Technology

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1
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 – Rev. 5/00
©2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions,
and package
• 12 row, 10 column addresses (R6)
13 row, 9 column addresses (N3)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
OPTIONS
MARKING
• Plastic Package
50-pin TSOP (400 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
4K
R6
8K
N3
Standard Refresh
None
Self Refresh
S*
• Operating Temperature Range
Commercial (0°C to +70°C)
None
Extended (-40°C to +85°C)
IT**
NOTE: 1. The “#” symbol indicates signal is active LOW.
*Contact factory for availability.
**Available only on MT4LC4M16R6 standard refresh device.
Part Number Example:
MT4LC4M16R6TG-5
PIN ASSIGNMENT (Top View)
DRAM
MT4LC4M16R6, MT4LC4M16N3
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
VCC
WE#
RAS#
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
VSS
CASL#
CASH#
OE#
NC
NC
NC/A12
A11
A10
A9
A8
A7
A6
VSS
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tPC
tAA
tCAC
tCAS
-5
84ns
50ns
20ns
25ns
13ns
8ns
-6
104ns
60ns
25ns
30ns
15ns
10ns
50-Pin TSOP
4 MEG x 16 EDO DRAM PART NUMBERS
REFRESH
PART NUMBER
ADDRESSING PACKAGE REFRESH
MT4LC4M16R6TG-x
4K
400-TSOP
Standard
MT4LC4M16R6TG-x S
4K
400-TSOP
Self
MT4LC4M16N3TG-x
8K
400-TSOP
Standard
MT4LC4M16N3TG-x S
8K
400-TSOP
Self
x = speed
MT4LC4M16R6
MT4LC4M16N3
Configuration
4 Meg x 16
4 Meg x 16
Refresh
4K
8K
Row Address
4K (A0-A11)
8K (A0-A12)
Column Addressing
1K (A0-A9)
512 (A0-A8)
A12 for N3 version, NC for R6 version.


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