8

4 Meg x 4 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D49_5V.p65 – Rev. 5/00

©2000, Micron Technology, Inc.

4 MEG x 4

FPM DRAM

NOTES

1.

2.

f = 1 MHz.

3.

rates. Specified values are obtained with

minimum cycle time and the outputs open.

4.

Enables on-chip refresh and address counters.

5.

The minimum specifications are used only to

indicate cycle time at which proper operation

over the full temperature range is ensured.

6.

An initial pause of 100µs is required after power-

up, followed by eight RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is ensured. The eight RAS# cycle

refresh requirement is exceeded.

7.

8.

measuring timing of input signals. Transition

9.

In addition to meeting the transition rate

specification, all input signals must transit

a monotonic manner.

from the last valid READ cycle.

12. Measured with a load equivalent to two TTL

13. If CAS# is LOW at the falling edge of RAS#, Q

will be maintained from the previous cycle. To

initiate a new cycle and clear the data-out

be met.

cycle.

output achieves the open circuit condition and

cycle and the data output will remain an open

³

WRITE and the data output will contain data

read from the selected cell. If neither of the

above conditions is met, the state of data-out is

indeterminate. OE# held HIGH and WE# taken

LOW after CAS# goes LOW result in a LATE

WRITE cycle.

19. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. If OE# is tied permanently LOW, LATE WRITE,

or READ-MODIFY-WRITE operations are not

permissible and should not be attempted.

21. A HIDDEN REFRESH may also be performed

after a WRITE cycle. In this case, WE# = LOW

and OE# = HIGH.

22. The 3ns minimum is a parameter guaranteed by

design.

23. Column address changed once each cycle.

width

£ 10ns, and the pulse width cannot be

£

10ns, and the pu lse width cannot be greater

than one third of the cycle rate.