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MT4LC16M4G3TG-5S Datasheet(PDF) 7 Page - Micron Technology |
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MT4LC16M4G3TG-5S Datasheet(HTML) 7 Page - Micron Technology |
7 / 22 page 7 16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D22_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc. 16 MEG x 4 EDO DRAM CAPACITANCE (Note: 2) PARAMETER SYMBOL MAX UNITS Input Capacitance: Address pins CI1 5pF Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7pF Input/Output Capacitance: DQ CIO 7pF AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Access time from column address tAA 25 30 ns Column-address setup to CAS# precharge tACH 12 15 ns Column-address hold time (referenced to RAS#) tAR 38 45 ns Column-address setup time tASC 0 0 ns Row-address setup time tASR 0 0 ns Column address to WE# delay time tAWD 42 49 ns 18 Access time from CAS# tCAC 13 15 ns Column-address hold time tCAH 8 10 ns CAS# pulse width tCAS 8 10,000 10 10,000 ns CAS# LOW to “Don’t Care” during Self Refresh tCHD 15 15 ns CAS# hold time (CBR Refresh) tCHR 8 10 ns 4 CAS# to output in Low-Z tCLZ 0 0 ns Data output hold after CAS# LOW tCOH 3 3 ns CAS# precharge time tCP 8 10 ns 13 Access time from CAS# precharge tCPA 28 35 ns CAS# to RAS# precharge time tCRP 5 5 ns CAS# hold time tCSH 38 45 ns CAS# setup time (CBR Refresh) tCSR 5 5 ns 4 CAS# to WE# delay time tCWD 28 35 ns 18 WRITE command to CAS# lead time tCWL 8 10 ns Data-in hold time tDH 8 10 ns 19 Data-in setup time tDS 0 0 ns 19 Output disable tOD 0 12 0 15 ns 23, 24 Output enable time tOE 12 15 ns 20 OE# hold time from WE# during tOEH 8 10 ns 24 READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH tOEHC 5 10 ns OE# HIGH pulse width tOEP 5 5 ns OE# LOW to CAS# HIGH setup time tOES 4 5 ns Output buffer turn-off delay tOFF 0 12 0 15 ns 17, 23 |
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