4

16 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D22_2.p65 – Rev. 5/00

©2000, Micron Technology, Inc.

16 MEG x 4

EDO DRAM

V

V

IH

IL

CAS#

V

V

IH

IL

RAS#

V

V

IH

IL

ADDR

ROW

COLUMN (A)

DON’T CARE

UNDEFINED

V

V

IH

IL

WE#

V

V

IOH

IOL

OPEN

DQ

tWPZ

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

V

V

IH

IL

OE#

VALID DATA (B)

t

WHZ

WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

t

WHZ

COLUMN (D)

VALID DATA (A)

COLUMN (B)

COLUMN (C)

INPUT DATA (C)

Figure 2

WE# Control of DQs

V

V

IH

IL

CAS#

V

V

IH

IL

RAS#

V

V

IH

IL

ADDR

ROW

COLUMN (A)

COLUMN (B)

V

V

IH

IL

OE#

V

V

IOH

IOL

OPEN

DQ

tOD

VALID DATA (B)

VALID DATA (A)

COLUMN (C)

VALID DATA (A)

tOE

VALID DATA (C)

COLUMN (D)

VALID DATA (D)

tOD

tOEHC

tOD

tOEP

tOES

The DQs go back to

The DQs remain High-Z

until the next CAS# cycle

The DQs remain High-Z

until the next CAS# cycle

Figure 1

OE# Control of DQs

The self refresh mode is terminated by driving RAS#

the completion of any internal refresh cycles that may

be in process at the time of the RAS# LOW-to-HIGH

transition. If the DRAM controller uses a distributed

CBR refresh sequence, a burst refresh is not required

upon exiting self refresh. However, if the DRAM con-

troller uses RAS#-ONLY or burst CBR refresh, all rows

prior to resuming normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced

standby level. The chip is preconditioned for the next

cycle during the RAS# HIGH time.

DRAM REFRESH (Continued)