11

16 Meg x 4 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D21_2.p65 – Rev. 5/00

©2000, Micron Technology, Inc.

16 MEG x 4

FPM DRAM

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

VALID D

OUT

VALID D

IN

ROW

COLUMN

ROW

V

V

IH

IL

CAS#

V

V

IH

IL

ADDR

V

V

IH

IL

V

V

IH

IL

DQ

V

V

IOH

IOL

V

V

IH

IL

RAS#

OPEN

OPEN

tOE

tOD

tCAC

tRAC

tAA

tCLZ

tDS

tDH

tAWD

tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC

tCAH

tAR

tASR

tRAD

tCRP

tRCD

tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

WE#

DON’T CARE

UNDEFINED

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

3

13

3

15

ns

13

15

ns

13

15

ns

50

60

ns

13

15

ns

8

10

ns

50

10,000

60

10,000

ns

18

20

ns

0

0

ns

30

40

ns

13

15

ns

131

155

ns

73

85

ns

13

15

ns

8

10

ns

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

25

30

ns

40

45

ns

0

0

ns

0

0

ns

48

55

ns

13

15

ns

8

10

ns

13

10,000

15

10,000

ns

3

3

ns

5

5

ns

50

60

ns

36

40

ns

13

15

ns

8

10

ns

0

0

ns