1

8 Meg x 8 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D19_2.p65 – Rev. 5/00

©2000, Micron Technology, Inc.

8 MEG x 8

FPM DRAM

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x8 pinout, timing, functions,

and packages

• 13 row, 10 column addresses (E1) or

12 row, 11 column addresses (B6)

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-

compatible

• FAST PAGE MODE (FPM) access

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64ms

• Optional self refresh (S) for low-power data

retention

OPTIONS

MARKING

• Refresh Addressing

4,096 (4K) rows

B6

8,192 (8K) rows

E1

• Plastic Packages

32-pin SOJ (400 mil)

DJ

32-pin TSOP (400 mil)

TG

• Timing

50ns access

-5

60ns access

-6

• Refresh Rates

Standard Refresh (64ms period)

None

Self Refresh (128ms period)

S*

NOTE: 1. The 8 Meg x 8 FPM DRAM base number

differentiates the offerings in one place—

MT4LC8M8E1. The fifth field distinguishes

various options: E1 designates an 8K refresh and

B6 designates a 4K refresh for FPM DRAMs.

2. The # symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC8M8E1DJ-5

DRAM

MT4LC8M8E1, MT4LC8M8B6

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/products/datasheets/dramds.html

8 MEG x 8 FPM DRAM PART NUMBERS

REFRESH

PART NUMBER

ADDRESSING

PACKAGE REFRESH

MT4LC8M8E1DJ-x

8K

SOJ

Standard

MT4LC8M8E1DJ-x S

8K

SOJ

Self

MT4LC8M8E1TG-x

8K

TSOP

Standard

MT4LC8M8E1TG-x S

8K

TSOP

Self

MT4LC8M8B6DJ-x

4K

SOJ

Standard

MT4LC8M8B6DJ-x S

4K

SOJ

Self

MT4LC8M8B6TG-x

4K

TSOP

Standard

MT4LC8M8B6TG-x S

4K

TSOP

Self

x = speed

**A12 on E1 version, NC on B6 version

32-Pin TSOP

DQ0

DQ1

DQ2

DQ3

NC

WE#

RAS#

A0

A1

A2

A3

A4

A5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

DQ7

DQ6

DQ5

DQ4

CAS#

OE#

A11

A10

A9

A8

A7

A6

32-Pin SOJ

DQ0

DQ1

DQ2

DQ3

NC

WE#

RAS#

A0

A1

A2

A3

A4

A5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

DQ7

DQ6

DQ5

DQ4

Vss

CAS#

OE#

A11

A10

A9

A8

A7

A6

PIN ASSIGNMENT (Top View)

KEY TIMING PARAMETERS

SPEED

-5

90ns

50ns

30ns

25ns

13ns

-6

110ns

60ns

35ns

30ns

15ns

GENERAL DESCRIPTION

The 8 Meg x 8 DRAMs are high-speed CMOS, dy-

namic random-access memory devices containing

67,108,864 bits organized in a x8 configuration. The

8 Meg x 8 DRAMs are functionally organized as 8,388,608

locations containing eight bits each. The 8,388,608

memory locations are arranged in 8,192 rows by 1,024

columns for the MT4LC8M8E1 or 4,096 rows by 2,048

columns for the MT4LC8M8B6. During READ or WRITE

cycles, each location is uniquely addressed via the

address bits. First, the row address is latched by the