KAF-1001 Image Sensor

www.truesenseimaging.com

Revision 1.1 PS-0033 Pg 9

Pin

Name

Description

Pin

Name

Description

1

Substrate

Substrate

14

φH21

Last Horizontal (Serial) CCD Phase - Split

Gate

2

φV2

Vertical (Parallel) CCD Clock – Phase 2

15

φH22

Last Horizontal (Serial) CCD Phase - Split

Gate

3

φV1

Vertical (Parallel) CCD Clock – Phase 1

16

φH1

Horizontal (Serial) CCD Clock - Phase 1

4

Substrate

Substrate

17

φH2

Horizontal (Serial) CCD Clock - Phase 2

5

VOUT2

Video Output from High Sensitivity Two-Stage Amplifier

18

N/C

No Connection

6

VDD2

High Sensitivity Two-Stage Amplifier Supply

19

N/C

No Connection

7

VLG

First Stage Load Transistor Gate for Two-Stage Amplifier

20

N/C

No Connection

8

VSS

Output Amplifier Return

21

φV2

Vertical (Parallel) CCD Clock – Phase 2

9

φR

Reset Clock

22

φV1

Vertical (Parallel) CCD Clock – Phase 1

10

VRD

Reset Drain

23

Guard

Guard Ring

11

VDD1

High Dynamic Range Single-Stage Amplifier Supply

24

φV1

Vertical (Parallel) CCD Clock – Phase 1

12

VOUT1

Video Output from High Dynamic Range Single-Stage

Amplifier

25

φV2

Vertical (Parallel) CCD Clock – Phase 2

13

OG

Output Gate

26

Substrate

Substrate

Notes:

1.

Pins 3, 22, and 24 must be connected together - only one Phase 1 clock driver is required.

2.

Pins 2, 21, and 25 must be connected together - only one Phase 2 clock driver is required.