KAF-1001 Image Sensor

www.truesenseimaging.com

Revision 1.1 PS-0033 Pg 7

Vlg

Floating

Diffusion

HCCD

Charge

Transfer

Source

Follower

#1

Source

Follower

#2

Vrd

R

Vog

H1L

H1

H2

VDD

Vout

H2

Figure 2: Output Schematic

An image is acquired when incident light, in the form of photons, falls on the array of pixels in the vertical CCD register

and creates electron-hole pairs (or simply electrons) within the silicon substrate. This charge is collected locally by the

formation of potential wells created at each pixel site by induced voltages on the vertical register clock lines (φV1,

φV2). These same clock lines are used to implement the transport mechanism as well. The amount of charge collected

at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength until

the potential well capacity is exceeded. At this point charge will 'bloom' into vertically adjacent pixels.

Integrated charge is transported to the output in a two-step process. Rows of charge are first shifted line by line into

the horizontal CCD. 'Lines' of charge are then shifted to the output pixel by pixel. Referring to the timing diagram,

integration of charge is performed with φV1 and φV2 held low. Transfer to horizontal CCD begins when φV1 is

brought high causing charge from the φV1 and φV2 gates to combine under the φV1 gate.

φV1 and φV2 now reverse their polarity causing the charge packets to 'spill' forward under the φV2 gate of the next

pixel. The rising edge of φV2 also transfers the first line of charge into the horizontal CCD. A second phase transition

places the charge packets under the φV1 electrode of the next pixel. The sequence completes when φV1 is brought

low. Clocking of the vertical register in this way is known as accumulation mode clocking. Next, the horizontal CCD

reads out the first line of charge using traditional complementary clocking (using φH1 and φH2 pins) as shown. The

falling edge of φH2 forces a charge packet over the output gate (OG) onto one of the output nodes (floating diffusion)

which controls the output amplifier. The cycle repeats until all lines are read.