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KAI-01050-FBA-FD-BA Datasheet(PDF) 4 Page - ON Semiconductor |
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KAI-01050-FBA-FD-BA Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 32 page KAI−01050 www.onsemi.com 4 Physical Description PGA Pin Description and Device Orientation Figure 3. PGA Package Pin Designations − Top View Pixel (1,1) 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 V3B V1B V4B VDDa V2B GND VOUTa Ra RDa H2SLa OGa H1Bb H2Bb H2Sb H1Sb N/C SUB H2Sa H1Sa H1Ba H2Ba 23 24 H2SLb OGb 25 26 27 28 29 30 31 32 V1B V4B VDDb V2B GND VOUTb Rb RDb 33 34 V3B ESD 68 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 ESD V4T V1T V2T VDDc VOUTc GND RDc Rc OGc H2SLc H2Bd H1Bd H1Sd H2Sd SUB N/C H1Sc H2Sc H2Bc H1Bc 46 45 OGd H2SLd 44 43 42 41 40 39 38 37 V4T V1T V2T VDDd VOUTd GND RDd Rd 36 35 DevID V3T 67 V3T Table 4. PGA PACKAGE PIN DESCRIPTION Pin Name Description 1 V3B Vertical CCD Clock, Phase 3, Bottom 3 V1B Vertical CCD Clock, Phase 1, Bottom 4 V4B Vertical CCD Clock, Phase 4, Bottom 5 VDDa Output Amplifier Supply, Quadrant a 6 V2B Vertical CCD Clock, Phase 2, Bottom 7 GND Ground 8 VOUTa Video Output, Quadrant a 9 Ra Reset Gate, Quadrant a 10 RDa Reset Drain, Quadrant a 11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a 12 OGa Output Gate, Quadrant a 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a 17 N/C No Connect 18 SUB Substrate 19 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 20 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b 21 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b 22 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b 23 H2SLb Horizontal CCD Clock, Phase 1, Storage, Last Phase, Quadrant b |
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