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MT9J003D00STMUC2CBC1-200 Datasheet(PDF) 11 Page - ON Semiconductor |
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MT9J003D00STMUC2CBC1-200 Datasheet(HTML) 11 Page - ON Semiconductor |
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11 / 77 page  MT9J003-DS Rev. E 5/15 EN 11 ©Semiconductor Components Industries, LLC,2015. MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor Signal Descriptions Signal Descriptions Table 1 provides signal descriptions for MT9J003 die. For pad location and aperture information, refer to the MT9J003 die data sheet. Table 1: Signal Descriptions Pad Name Pad Type Description EXTCLK Input Master clock input, 6–48 MHz. RESET_BAR (XSHUTDOWN) Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers are restored to their factory default settings. SCLK Input Serial clock for access to control and status registers. GPI[3:0] Input General purpose inputs. After reset, these pads are powered-down by default; this means that it is not necessary to bond to these pads. Any of these pads can be configured to provide hardware control of the standby, output enable, SADDR select, and shutter trigger functions. Can be left floating if not used. TEST Input Enable manufacturing test modes. It should not be left floating. It can be tied to ground or VDD_IO when used in parallel or HiSPi. It should be connected to DGND for normal operation of the CCP2 configured sensor, or connected to VDD_IO power for the MIPI®-configured sensor. SDATA I/O Serial data from READs and WRITEs to control and status registers. LINE_VALID Output LINE_VALID (LV) output. Qualified by PIXCLK. FRAME_VALID Output FRAME_VALID (FV) output. Qualified by PIXCLK. DOUT[11:0] Output Parallel pixel data output. Qualified by PIXCLK. PIXCLK Output Pixel clock. Used to qualify the LV, FV, and DOUT[11:0] outputs. FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used. SHUTTER Output Control for external mechanical shutter. Can be left floating if not used. VPP Supply Power supply used to program one-time programmable (OTP) memory. Disconnect pad when not programming or when feature is not used. VDD_TX0 Supply PHY power supply. Digital power supply for the MIPI or CCP2 serial data interface. ON Semiconductor recommends that VDD_TX0 is always tied to VDD when using an unpackaged sensor. VDD_SLVS Supply HiSPi power supply for data and clock output. This should be tied to VDD VDD_SLVS_TX Supply Digital power supply for the HiSPi I/O. VAA Supply Analog power supply. VAA_PIX Supply Analog power supply for the pixel array. AGND Supply Analog ground. VDD Supply Digital power supply. VDD_IO Supply I/O power supply. DGND Supply Common ground for digital and I/O. VDD_PLL Supply PLL power supply. GND_PLL Supply PLL ground. PIXGND Supply Pixel ground. SLVS_0P Output Lane 1 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock. SLVS_0N Output Lane 1 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock. SLVS_1P Output Lane 2 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock. SLVS_1N Output Lane 2 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock. SLVS_2P Output Lane 3 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock. SLVS_2N Output Lane 3 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock. |
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