MT9M024 datasheet(10/65 Pages) ONSEMI

Part #	MT9M024

Description	CMOS Digital Image Sensor

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Manufacturer	ONSEMI [ON Semiconductor]

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10 / 65 page

MT9M024_DS Rev. G Pub. 4/15 EN

10

©Semiconductor Components Industries, LLC,2015.

MT9M024: 1/3-Inch CMOS Digital Image Sensor

Functional Overview

Table 1:

Pin Descriptions, 9 x 9 mm, 63-ball iBGA

Name

iBGA Pin

Type

Description

SLVS0N

A2

Output

HiSPi serial data, lane 0, differential N.

SLVS0P

A3

Output

HiSPi serial data, lane 0, differential P.

SLVS1N

A4

Output

HiSPi serial data, lane 1, differential N.

SLVS1P

A5

Output

HiSPi serial data, lane 1, differential P.

STANDBY

A8

Input

Standby-mode enable pin (active HIGH).

VDD_PLL

B1

Power

PLL power.

SLVSCN

B2

Output

HiSPi serial DDR clock differential N.

SLVSCP

B3

Output

HiSPi serial DDR clock differential P.

SLVS2N

B4

Output

HiSPi serial data, lane 2, differential N.

SLVS2P

B5

Output

HiSPi serial data, lane 2, differential P.

VAA

B7, B8

Power

Analog power.

EXTCLK

C1

Input

External input clock.

VDD_SLVS

C2

Power

HiSPi power.

SLVS3N

C3

Output

HiSPi serial data, lane 3, differential N.

SLVS3P

C4

Output

HiSPi serial data, lane 3, differential P.

DGND

C5, D4, D5, E5, F5, G5, H5

Power

Digital ground.

VDD

A6, A7, B6, C6, D6

Power

Digital power.

AGND

C7, C8

Power

Analog ground.

SADDR

D1

Input

Two-Wire Serial address select.

SCLK

D2

Input

Two-Wire Serial clock input.

SDATA

D3

I/O

Two-Wire Serial data I/O.

VAA_PIX

D7, D8

Power

Pixel power.

LINE_VALID

E1

Output

Asserted when DOUT line data is valid.

FRAME_VALID

E2

Output

Asserted when DOUT frame data is valid.

PIXCLK

E3

Output

Pixel clock out. DOUT is valid on rising edge of this clock.

VDD_IO

E6, F6, G6, H6, H7

Power

I/O supply power.

DOUT8

F1

Output

Parallel pixel data output.

DOUT9

F2

Output

Parallel pixel data output.

DOUT10

F3

Output

Parallel pixel data output.

DOUT11

F4

Output

Parallel pixel data output (MSB)

TEST

F7

Input.

Manufacturing test enable pin (connect to DGND).

DOUT4

G1

Output

Parallel pixel data output.

DOUT5

G2

Output

Parallel pixel data output.

DOUT6

G3

Output

Parallel pixel data output.

DOUT7

G4

Output

Parallel pixel data output.

TRIGGER

G7

Input

Exposure synchronization input.

OE_BAR

G8

Input

Output enable (active LOW).

DOUT0

H1

Output

Parallel pixel data output (LSB)

DOUT1

H2

Output

Parallel pixel data output.

DOUT2

H3

Output

Parallel pixel data output.

DOUT3

H4

Output

Parallel pixel data output.

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