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MT9M034I12STM-DRBR Datasheet(PDF) 7 Page - ON Semiconductor |
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MT9M034I12STM-DRBR Datasheet(HTML) 7 Page - ON Semiconductor |
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7 / 56 page  MT9M034_DS Rev. G Pub. 4/15 EN 7 ©Semiconductor Components Industries, LLC,2015. MT9M034: 1/3-Inch CMOS Digital Image Sensor Functional Overview analog signal chain (providing offset correction and gain), and then through an analog- to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 20-bit per pixel value. A compressing mode is further offered to allow this 20-bit pixel value to be transmitted to the host system as a 12-bit value with close to zero loss in image quality. The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization signals. Notes: 1. 2. 3. 4. 5. 6. Figure 2: Typical Configuration: Parallel Pixel Data Interface Notes: 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- VDD Master clock (6–50 MHz) SDATA SCLK TEST FRAME_VALID DOUT [11:0] EXTCLK DGND Digital ground Analog ground Digital core power1 To controller From Controller LINE_VALID PIXCLK RESET_BAR VDD_IO Digital I/O power1 VAA VAA_PIX Analog power1 VDD_PLL PLL power1 Analog power1 VAA_PIX VDD_IO VDD_PLL VDD VAA TRIGGER OE_BAR STANDBY AGND SADDR |
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