(

)

L

)

on

(

DS

OUT

(min)

OUT

(min)

IN

R

R

I

V

V

+

+

=

ON

OUT

IN

peak

LPSM

t

L

V

V

I

×

-

=

)

(

)

(

ns

V

V

t

IN

OUT

ON

400

×

=

TPS62150A-Q1, TPS62153A-Q1

www.ti.com

SLVSCC3 – MAY 2014

Feature Description (continued)

(1)

For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The

peak inductor current in Power Save Mode can be approximated by:

(2)

regardless of the load current. The device maintains output regulation in PWM mode.

10.3.3 100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to

the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch

100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set

point. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of

battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output

voltage level, can be calculated as:

spacing

(3)

where

10.3.4 Enable / Shutdown (EN)

When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a

shutdown current of typically 1.5µA. During shutdown, the internal power MOSFETs as well as the entire control

circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must

be set externally to High or Low. An internal pull-down resistor of about 400k

Ω is connected and keeps EN logic

low, if Low is set initially and then the pin gets floating. It is disconnected if the pin is set High.

Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple

power rails.

10.3.5 Soft Start / Tracking (SS/TR)

The internal soft start circuitry controls the output voltage slope during startup, avoiding excessive inrush current

and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-impedance

power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of

about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. See

Figure 25 and Figure 26 for typical startup operation.

Using very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. The

TPS6215xA-Q1 can start into a pre-biased output. During monotonic pre-biased startup, both of the power

MOSFETs are not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias

voltage. If the device is set to shutdown (EN=GND), undervoltage lockout or thermal shutdown, an internal

resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new startup

sequence as set by the SS/TR connection.

Copyright © 2014, Texas Instruments Incorporated

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