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MT9V024IA7XTC-DP Datasheet(PDF) 8 Page - ON Semiconductor |
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MT9V024IA7XTC-DP Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 62 page  MT9V024_DSRev. G Pub. 4/15 EN 7 ©Semiconductor Components Industries, LLC, 2015. MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor Ball Descriptions Ball Descriptions Table 1: Ball Descriptions 52-Ball IBA Numbers Symbol Type Description Note H7 RSVD Input Connect to DGND.1 D2 SER_DATAIN_N Input Serial data in for stereoscopy (differential negative). Tie to 1K pull-up (to 3.3V) in non-stereoscopy mode. D1 SER_DATAIN_P Input Serial data in for stereoscopy (differential positive). Tie to DGND in non-stereoscopy mode. C2 BYPASS_CLKIN_N Input Input bypass shift-CLK (differential negative). Tie to 1K pull-up (to 3.3V) in non-stereoscopy mode. C1 BYPASS_CLKIN_P Input Input bypass shift-CLK (differential positive). Tie to DGND in non- stereoscopy mode. H3 EXPOSURE Input Rising edge starts exposure in snapshot and slave modes. H4 SCLK Input Two-wire serial interface clock. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. H6 OE Input DOUT enable pad, active HIGH. 2 G7 S_CTRL_ADR0 Input Two-wire serial interface slave address select (see Table 4 on page 12). H8 S_CTRL_ADR1 Input Two-wire serial interface slave address select (see Table 4 on page 12). G8 RESET_BAR Input Asynchronous reset. All registers assume defaults. F8 STANDBY Input Shut down sensor operation for power saving. A5 SYSCLK Input Master clock (26.6 MHz; 13 MHz – 27 MHz). G4 SDATA I/O Two-wire serial interface data. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. G3 STLN_OUT I/O Output in master mode —start line sync to drive slave chip in- phase; input in slave mode. G5 STFRM_OUT I/O Output in master mode —start frame sync to drive a slave chip in- phase; input in slave mode. H2 LINE_VALID Output Asserted when DOUT data is valid. G2 FRAME_VALID Output Asserted when DOUT data is valid. E1 DOUT5 Output Parallel pixel data output 5. F1 DOUT6 Output Parallel pixel data output 6. F2 DOUT7 Output Parallel pixel data output 7. G1 DOUT8 Output Parallel pixel data output 8 H1 DOUT9 Output Parallel pixel data output 9. H5 ERROR Output Error detected. Directly connected to STEREO ERROR FLAG. G6 LED_OUT Output LED strobe output. B7 DOUT4 Output Parallel pixel data output 4. A8 DOUT3 Output Parallel pixel data output 3. A7 DOUT2 Output Parallel pixel data output 2. B6 DOUT1 Output Parallel pixel data output 1. A6 DOUT0 Output Parallel pixel data output 0. B5 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. |
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